## 386 exception vectors. Nothing like 8086 equivalents. 32 bits, for one thing.

   There are two sources for external interrupts and two sources for exceptions:
    1. Interrupts
          + Maskable interrupts, which are signalled via the INTR pin.
          + Nonmaskable interrupts, which are signalled via the NMI (Non-Maskable
            Interrupt) pin.
    2. Exceptions
          + Processor detected. These are further classified as faults, traps, and
            aborts.
          + Programmed. The instructions INTO, INT 3, INT n, and BOUND can trigger
            exceptions. These instructions are often called "software interrupts",
            but the processor handles them as exceptions.


   The identifiers of the maskable interrupts are determined by external interrupt
   controllers (such as Intel's 8259A Programmable Interrupt Controller) and
   communicated to the processor during the processor's interrupt-acknowledge
   sequence. The numbers assigned by an 8259A PIC can be specified by software. Any
   numbers in the range 32 through 255 can be used. Table 9-1 shows the assignment
   of interrupt and exception identifiers.

Table 9-1. Interrupt and Exception ID Assignments, ## system level version.

Identifier   Description

0            Divide error
1            Debug exceptions
2            Nonmaskable interrupt
3            Breakpoint (one-byte INT 3 instruction)
4            Overflow (INTO instruction)
5            Bounds check (BOUND instruction)
6            Invalid opcode
7            Coprocessor not available
8            Double fault
9            (reserved)
10           Invalid TSS
11           Segment not present
12           Stack exception
13           General protection
14           Page fault			
15           (reserved)
16           Coprecessor error
17-31        (reserved)
32-255       Available for external interrupts via INTR pin


                          9.2 Enabling and Disabling Interrupts
9.2.1 NMI Masks Further NMIs
9.2.2 IF Masks INTR

   The IF (interrupt-enable flag) controls the acceptance of external interrupts
   signalled via the INTR pin. When IF=0, INTR interrupts are inhibited; when IF=1,
   INTR interrupts are enabled. As with the other flag bits, the processor clears
   IF in response to a RESET signal. The instructions CLI and STI alter the setting
   of IF.
   CLI (Clear Interrupt-Enable Flag) and STI (Set Interrupt-Enable Flag) explicitly
   alter IF (bit 9 in the flag register). These instructions may be executed only
   if CPL <= IOPL. A protection exception occurs if they are executed when CPL >
   IOPL.
   The IF is also affected implicitly by the following operations:
     * The instruction PUSHF stores all flags, including IF, in the stack where
       they can be examined.
     * Task switches and the instructions POPF and IRET load the flags register;
       therefore, they can be used to modify IF.
     * Interrupts through interrupt gates automatically reset IF, disabling
       interrupts. (Interrupt gates are explained later in this chapter.)

9.2.4 MOV or POP to SS Masks Some Interrupts and Exceptions

   Software that needs to change stack segments often uses a pair of instructions;
   for example:
		MOV SS, AX
		MOV ESP, StackTop

   If an interrupt or exception is processed after SS has been changed but before
   ESP has received the corresponding change, the two parts of the stack pointer
   SS:ESP are inconsistent for the duration of the interrupt handler or exception
   handler.

   To prevent this situation, the 80386, after both a MOV to SS and a POP to SS
   instruction, inhibits NMI, INTR, debug exceptions, and single-step traps at the
   instruction boundary following the instruction that changes SS. Some exceptions
   may still occur; namely, page fault and general protection fault. Always use the
   80386 LSS instruction, and the problem will not occur.

                9.3 Priority Among Simultaneous Interrupts and Exceptions

   If more than one interrupt or exception is pending at an instruction boundary,
   the processor services one of them at a time. The priority among classes of
   interrupt and exception sources is shown in Table 9-2. The processor first
   services a pending interrupt or exception from the class that has the highest
   priority, transferring control to the first instruction of the interrupt
   handler. Lower priority exceptions are discarded; lower priority interrupts are
   held pending. Discarded exceptions will be rediscovered when the interrupt
   handler returns control to the point of interruption.

                             9.4 Interrupt Descriptor Table

   The interrupt descriptor table (IDT) associates each interrupt or exception
   identifier with a descriptor for the instructions that service the associated
   event. Like the GDT and LDTs, the IDT is an array of 8-byte descriptors. Unlike
   the GDT and LDTs, the first entry of the IDT may contain a descriptor. To form
   an index into the IDT, the processor multiplies the interrupt or exception
   identifier by eight. Because there are only 256 identifiers, the IDT need not
   contain more than 256 descriptors. It can contain fewer than 256 entries;
   entries are required only for interrupt identifiers that are actually used.

   The IDT may reside anywhere in physical memory. As Figure 9-1 shows, the
   processor locates the IDT by means of the IDT register (IDTR). The instructions
   LIDT and SIDT operate on the IDTR. Both instructions have one explicit operand:
   the address in memory of a 6-byte area. Figure 9-2 shows the format of this
   area.
   LIDT (Load IDT register) loads the IDT register with the linear base address and
   limit values contained in the memory operand. This instruction can be executed
   only when the CPL is zero. It is normally used by the initialization logic of an
   operating system when creating an IDT. An operating system may also use it to
   change from one IDT to another.

   SIDT (Store IDT register) copies the base and limit value stored in IDTR to a
   memory location. This instruction can be executed at any privilege level.

Table 9-2. Priority Among Simultaneous Interrupts and Exceptions

Priority   Class of Interrupt or Exception
	HIGHEST    	Faults except debug faults
			Trap instructions INTO, INT n, INT 3
			Debug traps for this instruction
			Debug faults for next instruction
			NMI interrupt
	LOWEST     	INTR interrupt


##Causes

* divide errors
   The instruction INT generates an interrupt whenever it is executed;
* A breakpoint exception results when the instruction INT 3 is executed.

     * An overflow exception results when the INTO instruction is executed and the
       OF (overflow) flag is set (after an arithmetic operation that set the OF
       flag ) . (Refer to Chapter 3 for a discussion of INTO) .
     * A bounds check exception results when the BOUND instruction is executed and
       the array index it checks falls outside the bounds of the array . (Refer to
       Chapter 3 for a discussion of the BOUND instruction. )
     * Invalid opcodes may be used by some applications to extend the instruction
       set. In such a case, the invalid opcode exception presents an opportunity to
       emulate the opcode.
     * The "coprocessor not available" exception occurs if the program contains
       instructions for a coprocessor, but no coprocessor is present in the system.
     * A coprocessor error is generated when a coprocessor detects an illegal
       operation.

