--------V-P03C003C1--------------------------
PORT 03C0-03C1 - EGA/VGA - ATTRIBUTE CONTROLLER
Range:  PORT 03C0h or PORT 02C0h (alternate EGA)
SeeAlso: PORT 03C2h,PORT 03D0h,#P0718

03C0  rW  ATC index/data register
                Every write access to this register will toggle an internal
                  index/data selection flipflop, so that consecutive writes to
                  index & data is possible through this port. To get a defined
                  start condition, each read access to the input status register                  #1 (3BAh in mono / 3DAh in color) resets the flipflop to load
                  index. If values are changed during the vertical retrace
                  period only no flicker will occur.
                  period only no flicker will occur.
                index register (flipflop reset to 'index'): (default 20h)
                  bit7-6: reserved
                  bit5  : 0=CPU access (screen dark),
                          1=video access to registers
                  bit4-0: index in ATC (0..31)

                indexed registers in ATC (flipflop set to 'data'): (see #P0662)
03C1  R-  (VGA) ATC index/data read register

(Table P0662)
Values for EGA/VGA indexed registers in ATC:
 00h-0Fh 16 palette registers (see #P0663)
 10h    mode control register (see #P0664)
 11h    (EGA) overscan color register (see #P0665) (default: 00h)
 11h    (VGA) overscan color register (see #P0666) (default: 00h)
 12h    color enable register (see #P0667)
 13h    horizontal pixel panning register
        bit7-4: reserved
        bit3-0: horizontal pixel panning
 14h    (VGA) color select register (default: 00h)
        bit7-4: reserved
        bit3  : s-color 7
        bit2  : s-color 6
        bit1  : s-color 5 (only with 16 pages  16 regs)
        bit0  : s-color 4 (only with 16 pages  16 regs)
 16h    ET3000, ET4000 only: ATC miscellanenous
        (at least on ET4000 'key' protected)
        This register is also supported by ET3000, but the
          description is proved for ET4000 only.
        bit7  : bypass the internal palette
                (e.g. for HiColor modes with Sierra RAMDACs)
        bit6  : reserved
        bit5-4: select high resolution / color mode
        bit3-0: reserved
SeeAlso: #P0670,#P0700

Bitfields for EGA/VGA indexed ATC palette register:
Bit(s)  Description     (Table P0663)
 7-6    reserved
 5      secondary red video
 4      secondary green/intensity video
 3      secondary blue/mono video
 2      primary red video
 1      primary green video
 0      primary blue video
SeeAlso: #P0662

Bitfields for EGA/VGA ATC mode control register:
Bit(s)  Description     (Table P0664)
 7      (VGA) SB/SG select (0=4 pages of 64 regs, 1=16 pages of 16 regs)
 6      (VGA) PELCLK/2 (0=4bit color, 1=8bit color)
 5      (VGA) enable pixel panning (0=all, 1=up to line compare register value)
 4      reserved
 3      background intensity (0=16 colors, 1=blink)
 2      line graphics enable (0=background, 1=line 8=9)
 1      1=mono, 0=color select
 0      1=graphics, 0=text select
SeeAlso: #P0662

Bitfields for EGA overscan color register:
Bit(s)  Description     (Table P0665)
 7-6    reserved
 5      secondary red (SR)
 4      secondary green (SR) / intensity
 3      secondary blue (SB)
 2      primary red (PR)
 1      primary green (PG)
 0      primary blue (PB)
SeeAlso: #P0662,#P0666

Bitfields for VGA overscan color register:
Bit(s)  Description     (Table P0666)
 7      secondary intensity border color (SI)
 6      secondary red (SR)
 5      secondary green (SG)
 4      secondary blue (SB)
 3      intensity border color (PI)
 2      primary red (PR)
 1      primary green (PG)
 0      primary blue (PB)
SeeAlso: #P0662,#P0665

Bitfields for EGA/VGA color enable register:
Bit(s)  Description     (Table P0667)
 7-6    reserved
 5-4    diagnose / video status select
        EGA:            VGA, ET4000:
        00b = PR/PB        PR/PB
        01b = SB/PG        SG/SB
        10b = SR/SG        PI/PG
        11b = reserved     SI/SR
 3      enable plane 3
 2      enable plane 2
 1      enable plane 1
 0      enable plane 0
SeeAlso: #P0662


--------V-P03C203CF--------------------------
PORT 03C2-03CF - EGA/VGA - MISCELLANEOUS REGISTERS
Range:  PORT 03C2h or PORT 02C2h (alternate EGA)
SeeAlso: PORT 03C0h,PORT 03C4h,PORT 03C6h,PORT 03D0h

03C2  R-  input status 0 register (see #P0668)
03C2  -W  miscellaneous output register (see #P0669)
03C3  RW  (VGA) video subsystem enable (see also PORT 46E8h)
                for IBM, motherboard VGA only
                         bit7-4=0: reserved
                         bit3    : select video subsystem (address 46E8h)
                         bit2-1  : reserved
                         bit0    : select video subsystem (address 03C3h)

Bitfields for EGA/VGA input status 0 register:
Bit(s)  Description     (Table P0668)
 7      (VGA) vertical retrace interrupt is pending
        (EGA) =0 vertical retrace in progress
 6-5    (VGA) reserved (0)
 6      (EGA and ET4000) feature control 1 (pin17)
 5      (EGA and ET4000) feature control 0 (pin19)
 4      (VGA) monitor sense signal is asserted
 4      (EGA, Genoa SuperEGA) DIP switch sense
        0=closed, 1=open/switches readable
 3-0    reserved (0)

Bitfields for EGA/VGA miscellaneous output register:
Bit(s)  Description     (Table P0669)
---Genoa SuperEGA in all emulation modes---
 7-6: vertical resolution
        00 (EGA) 200 lines
        01 (VGA) 400 lines
        10 (EGA/VGA) 350 lines
        11 (VGA) 480 lines
------
 7      vertical sync polarity (0=positive, 1=negative)
 6      horizontal sync polarity (0=positive, 1=negative)
 5      odd/even pagebit (=1 select second 64K memory page)
 4      EGA: 0=video driver on,
             1=video driver off (feature connector used)
 3-2    pixelclock
        00 14/25.175 MHz (EGA/VGA)
        01 16/28.322 Mhz (EGA/VGA)
        10 (EGA/VGA) external clock (EGA)
        10 (Genoa SuperEGA) 39Mhz
        11 (EGA/VGA) reserved
        11 (Genoa SuperEGA) 26.824Mhz
        11 (S3 Trio32/Trio64) enable clock programming via sequencer registers
                  12h and 13h
 1      enable CPU RAM access
 0      CRTC port address
        0=3B4h mono
        1=3D4h color
           (color EGA: enable feature control at 3DAh,status reg 1 at 3D2h)
----------P03C403C5--------------------------
PORT 03C4-03C5 - EGA/VGA - SEQUENCER REGISTERS
Range:  PORT 03C4h or PORT 02C4h (alternate EGA)
SeeAlso: PORT 03C0h,PORT 03C2h,PORT 03C4h"Cirrus",PORT 03C4h"S3"
SeeAlso: PORT 03C4h"Tseng",PORT 03C6h,PORT 03D0h

03C4  -W  EGA   TS index register
                bit7-3 : reserved (VGA only)
                bit2-0 : current TS index
03C4  RW  VGA   sequencer register index (see #P0670)
03C5  -W  EGA   TS data register
03C5  RW  VGA   sequencer register data

(Table P0670)



PORT 03D4-03D5 - COLOR VIDEO - CRT CONTROL REGISTERS

03D4  rW  CRT (6845) register index   (CGA/MCGA/color EGA/color VGA)
        selects which register (0-11h) is to be accessed through 03D5
        this port is r/w on some VGA, e.g. ET4000
            bit 7-6 =0: (VGA) reserved
            bit 5   =0: (VGA) reserved for testage
            bit 4-0   : selects which register is to be accessed through 03D5
03D5  -W  CRT (6845) data register   (CGA/MCGA/color EGA/color VGA) (see #P0708)        selected by PORT 03D4h. registers 0C-0F may be read
          (see also PORT 03B5h)
        MCGA, native EGA and VGA use very different defaults from those
          mentioned for the other adapters; for additional notes and
          registers 00h-0Fh and EGA/VGA registers 10h-18h and ET4000
          registers 32h-37h see PORT 03B5h (see #P0654)
        registers 10h-11h on CGA, EGA, VGA and 12h-14h on EGA, VGA are
          conflictive with MCGA (see #P0710)

(Table P0708)
Values for EGA/VGA+ CRT Controller register index:
 00h-0Fh        same as MDA/CGA (see #P0654)
 10h R- native VGA with bit7=1 in end horizontal blanking (03h) and ET4000:
               start vertical retrace
 10h -W start vertical retrace
 11h R- native VGA with bit7=1 in end horizontal blanking (03h):
               end vertical retrace
 11h -W end vertical retrace
               bit7  : VGA: protection bit
                            =0 enable write access to 00h-07h
                            =1 read only regs 00h-07h with the exception
                               of bit4 in 07h. ET4000: protect 35h also.
               bit6  : VGA: =0 three, =1 five refreshcycles/line
                       ET4000: reserved
               bit5=0: (MCGA also) enable vertical interrupt
               bit4=0: (MCGA also) clear vertical interrupt
                   =1:             no effect
               bit3-0: (MCGA also) vertical retrace end
 12h    vertical display end register
 13h    row offset register
               logical screen line width in
                byte mode : bytes/(line/2)
                word mode : bytes/(line/4)
                dword mode: bytes/(line/8)
 14h    underline location register
               bit7: reserved (0)
               bit6: (VGA) 0=word-mode, 1=dword-mode (see 17h, bit6)
               bit5: (VGA) 0=standard address counter clock
                           1=address counter clock/4 (see 17h, bit3)
               bit4-0: horizontal underline row scan
 15h    (EGA,VGA) start vertical blanking-1
 16h    (EGA,VGA) end vertical blanking register
               bit7-5 : EGA: reserved, but used on original EGA???
               bit4-0 : end vertical blanking
 17h    (EGA,VGA) "CR17" mode control register (see #P0657)
 18h    (EGA,VGA) "CR18" line compare register
 19h    Genoa SuperEGA only: double scan control
               at 3B5h only in MDA, HGC emulation, but at 3D5h even in
               mono EGA modes.
               bit7-5 : reserved
               bit4   : HR/VR width adjust flag for double scan mode
               bit3-1 : 1=test, 0=normal
               bit0   : double scan enable
 22h    (VGA) "CR22" CPU Latch Data Register (read-only)
 24h    (VGA) "CR24" Attribute Controller Toggle register (R-O) (see #P0709)
 3xh    (VGA)  !!!chips\64200.pdf p.57
Notes:  registers 10h-14h on the MCGA have conflicting uses (see #P0710)
        registers 22h,24h, and 3xh exist on the standard IBM VGA but were not
          documented

