There's a pdf on the net.

PIT Programmable Interval Timer stuff; NMI, speaker, "Dos system clock",
and stuff running off those, such as the process switcher. Factored by
use, since the 6 PIT timers on a PC are more or less implemented by use
rather than as general purpose clocks, i.e. they are what they do more
than they are timers. They are hardwired a certain way, and it's fugly.

A PIT is 3 16-bit countdown timers that can run in several timing modes.
The PC runs these at 1.19Mhz (Ye Olde 4.77Mhz /4). The lowest frequency is
thus just over 18hz. Timer 0 of PIT1 is wired to IRQ 0, normally the
highest priority maskable interrupt. Timer 2 is wired to the PC speaker
for a beep "oscillator". Remarkable audio stunts have been done with that.

Other clocks on a PC that aren't PITs include the CMOS calendar clock,
which is also wired to a CPU interrupt. Then there's PCI clocks and so on,
but those might not be as ubiquitous or as consistantly located as thePITs
and CMOS clock.

The counters are tick-before-test, so a count of zero is effectively
0xffff, giving the approximately 18hz minimum frequency, "Dos system
clock".

ports
any PC	PIT1=0x40
EISA+	PIT2=0x48

context

offset
+0  	R/W  
	counter 0
		PIT1	wired to IRQ 0, often used as "the system timer"
		PIT2	wired to the CPU non-maskable interrupt. Yow. 
 
+1	R/W
	counter 1
		PIT1    DRAM refresh counter
		Otherwise useless, in other words. AFAICT. 
			Leave it like the BIOS left it.
		PIT2	unused. (unavailable? unwired at all?)
			Not WIRED to anything, but might be ticking and
				read/writeable
			
+2  	R/W
	counter 2
		PIT1	speaker beeper
		PIT2	CPU speed control  ?
			Not WIRED to anything, but might be ticking and
				read/writeable

+3  	WRITE-READBACK
	mode port, control word register
	Bit(s)
	 7-6    counter select
	        00  counter 0 select
	        01  counter 1 select
	        10  counter 2 select
	        11  (8253) reserved
	            (8254) read back counter
			Bit(s)
			 7      PIN status of OUTx Pins (1=high, 0=low)
			 6      counter start value loaded
			        0: yes, so counter latch is valid to be read
		        	1: no, wait for counter latch to be set 
							(may last a while)
			5-0     counter mode, same as bits 5-0 at +3
		---if counter select---
			 5-4  counter access
			        00  counter latch command
			        01  read/write counter bits 0-7 only
			        10  read/write counter bits 8-15 only
			        11  read/write counter bits 0-7 first, 
						then 8-15
			 3-1  counter mode
			        000  - zero-detection interrupt
			        001  - programmable one-shot
			        x10  - rate generator
			        x11  - square wave generator
			                counts down twice by two at a time; 
					  latch status and check
			                  value of OUT pin to determine which 
					  half-cycle is active
			                  divisor factor 3 not allowed!
			        100 mode 4 select - software triggered strobe
			        101 mode 5 select - hardware triggered strobe
			 0    counting style
			        0  binary counter 16 bits
			        1  BCD counter (4 decades)
		---if read back---
			 5-4    what to read
			        00 counter status, then value
			        01 counter value
			        10 counter status
			        11 reserved
			 3      select counter 2
			 2      select counter 1
			 1      select counter 0
			 0      reserved (0)

After issuing a read back 'get status' command, any new read back command
is ignored until the status is read from all selected counters.

Once a control word has been written (+3), it must be followed
immediately by performing the corresponding action to the counter
registers (+0 <-> +2).

During normal operation mode +0 <-> +2 set the counter values on write and
get the current counter value on read. In 16bit modes two consequtive
writes/reads must be issued, first with the low byte, followed by the high
byte. In 8254 read back modes, all selected counters and status are
latched and must be read out completely before normal operation is valid
again. Each counter switches back to normal operation after read out.  
In 'get status and counter' mode the first byte read is the status,
followed by one or two counter values. Note that 16-bit reads performed
without using the "latch" command will get the current high/low portion of
the counter at the instant of the port read, so it is possible for the low
part of the counter to wrap around before the high part gets read,
resulting in a significant measurement error


