Non-Maskable Interrupt

NMI is a pin on an x86. On a PC AT and later it's triggerable by timer0 of
PIT2. On EISA and later there's a watchdog timer doodad affiliated with
that timer, and also a software trigger for NMI without the clock.

NMI will be the basis of Ha3sm periodic realtime services. A PIT can go to
1.19Mhz. Realtime reflexes have to be snappy. They are the most
speed-critical code in the system. The default reflex will be to increment
a 64-bit counter and bail. If I get into a polymodal OS, the rtNMI will
have a handler in each mode. They go here. Stuff that is virtualized on
top of NMI can refer to this area with symlinks I guess.

NMI is maskable with external gates accessed as bit 7 on the wallclock
port. Leonardo DaVinci had apparently left IBM by then. He wasn't there
when they soldered the GATE pins of the spare timers to GND either, I'm
quite sure.

