L PICprogram

# ICW1
       = `binary 10001` to A	# latched IRr bits
				#  ("edge-triggered"), 
				#   8259 __A__ using ICW4,
				#    cascaded
	= byte 0x20 to D
	send byte		# begin 4-write sequence to master
	=  byte 0xa0 to D
	send byte		# and slave

# 2  				unIBM the IRQ assignments. See also ./ABOUT

	=  byte $((firstIRQ)) to A
	=  byte 0x21 to D
	send byte
	=  byte $((firstIRQ+8)) to A
	=  byte 0xa1 to D
	send byte

# 3 
       =  byte 4 to A		# tell master that slave is on it's 2-wire
       =  byte 0x21 to D
       send byte
       =  byte 2 to A		# tell slave it's on master's 2
       =  byte 0xa1 to D
       send byte
# 4
       =  byte 1 to A			# x86 mode, not 8085
       =  byte 0x21 to D
       send byte
       =  byte 0xa1 to D
       send byte



#	prioritizeable (Programmable) Interrupt Controllers
##	program the PICs

# The way I read the INTeL 8259A pdf, "edge-triggered" looks fine,
#  perhaps less lossy than level-triggered, and either should be
#   perfectly shareable. What I want is "latched", which is 
#    what "edge-triggered" is. Don't forget to EOIRQ. 

# This is a very standard setup. I looked hard for something advantageous,
#  and nothing clever emerged.
