ARMLoadStoreOptimizer.cpp File Reference

#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMRegisterInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"

Include dependency graph for ARMLoadStoreOptimizer.cpp:

Go to the source code of this file.

Defines
#define	DEBUG_TYPE   "arm-ldst-opt"
Functions
	STATISTIC (NumLDMGened,"Number of ldm instructions generated")
	STATISTIC (NumSTMGened,"Number of stm instructions generated")
	STATISTIC (NumFLDMGened,"Number of fldm instructions generated")
	STATISTIC (NumFSTMGened,"Number of fstm instructions generated")
FunctionPass *	llvm::createARMLoadStoreOptimizationPass ()
static int	getLoadStoreMultipleOpcode (int Opcode)
static bool	mergeOps (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, SmallVector< std::pair< unsigned, bool >, 8 > &Regs, const TargetInstrInfo *TII)
static ARMCC::CondCodes	getInstrPredicate (MachineInstr *MI, unsigned &PredReg)
static bool	isMatchingDecrement (MachineInstr *MI, unsigned Base, unsigned Bytes, ARMCC::CondCodes Pred, unsigned PredReg)
static bool	isMatchingIncrement (MachineInstr *MI, unsigned Base, unsigned Bytes, ARMCC::CondCodes Pred, unsigned PredReg)
static unsigned	getLSMultipleTransferSize (MachineInstr *MI)
static bool	mergeBaseUpdateLSMultiple (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool &Advance, MachineBasicBlock::iterator &I)
static unsigned	getPreIndexedLoadStoreOpcode (unsigned Opc)
static unsigned	getPostIndexedLoadStoreOpcode (unsigned Opc)
static bool	mergeBaseUpdateLoadStore (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const TargetInstrInfo *TII, bool &Advance, MachineBasicBlock::iterator &I)
static bool	isMemoryOp (MachineInstr *MI)

---

Define Documentation

#define DEBUG_TYPE   "arm-ldst-opt"

Definition at line 15 of file ARMLoadStoreOptimizer.cpp.

---

Function Documentation

static ARMCC::CondCodes getInstrPredicate	(	MachineInstr *	MI,
		unsigned &	PredReg
	)			[static]

getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL. It also returns the condition code register by reference.

Definition at line 250 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARMCC::AL, llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by isMatchingDecrement(), isMatchingIncrement(), mergeBaseUpdateLoadStore(), and mergeBaseUpdateLSMultiple().

static int getLoadStoreMultipleOpcode

(

int

Opcode

)

[static]

Definition at line 86 of file ARMLoadStoreOptimizer.cpp.

Referenced by mergeOps().

static unsigned getLSMultipleTransferSize

(

MachineInstr *

MI

)

[inline, static]

Definition at line 285 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::getAM5Offset(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by mergeBaseUpdateLoadStore(), and mergeBaseUpdateLSMultiple().

static unsigned getPostIndexedLoadStoreOpcode

(

unsigned

Opc

)

[static]

Definition at line 428 of file ARMLoadStoreOptimizer.cpp.

Referenced by mergeBaseUpdateLoadStore().

static unsigned getPreIndexedLoadStoreOpcode

(

unsigned

Opc

)

[static]

Definition at line 415 of file ARMLoadStoreOptimizer.cpp.

Referenced by mergeBaseUpdateLoadStore().

static bool isMatchingDecrement	(	MachineInstr *	MI,
		unsigned	Base,
		unsigned	Bytes,
		ARMCC::CondCodes	Pred,
		unsigned	PredReg
	)			[inline, static]

Definition at line 261 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::getAM2Offset(), llvm::MachineOperand::getImm(), getInstrPredicate(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by mergeBaseUpdateLoadStore(), and mergeBaseUpdateLSMultiple().

static bool isMatchingIncrement	(	MachineInstr *	MI,
		unsigned	Base,
		unsigned	Bytes,
		ARMCC::CondCodes	Pred,
		unsigned	PredReg
	)			[inline, static]

Definition at line 273 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::getAM2Offset(), llvm::MachineOperand::getImm(), getInstrPredicate(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by mergeBaseUpdateLoadStore(), and mergeBaseUpdateLSMultiple().

static bool isMemoryOp

(

MachineInstr *

MI

)

[static]

isMemoryOp - Returns true if instruction is a memory operations (that this pass is capable of operating on).

Definition at line 541 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().

static bool mergeBaseUpdateLoadStore	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const TargetInstrInfo *	TII,
		bool &	Advance,
		MachineBasicBlock::iterator &	I
	)			[static]

mergeBaseUpdateLoadStore - Fold proceeding/trailing inc/dec of base register into the LDR/STR/FLD{D|S}/FST{D|S} op when possible:

Definition at line 443 of file ARMLoadStoreOptimizer.cpp.

References add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::ARM_AM::db, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::TargetInstrInfo::get(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Opc(), llvm::ARM_AM::getAM5Offset(), llvm::ARM_AM::getAM5Opc(), llvm::MachineOperand::getImm(), getInstrPredicate(), getLSMultipleTransferSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getPostIndexedLoadStoreOpcode(), getPreIndexedLoadStoreOpcode(), llvm::MachineOperand::getReg(), llvm::ARM_AM::ia, llvm::MachineOperand::isKill(), isMatchingDecrement(), isMatchingIncrement(), MI, llvm::next(), llvm::ARM_AM::no_shift, llvm::prior(), and sub().

static bool mergeBaseUpdateLSMultiple	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		bool &	Advance,
		MachineBasicBlock::iterator &	I
	)			[static]

mergeBaseUpdateLSMultiple - Fold proceeding/trailing inc/dec of base register into the LDM/STM/FLDM{D|S}/FSTM{D|S} op when possible:

stmia rn, <ra, rb, rc> rn := rn + 4 * 3; => stmia rn!, <ra, rb, rc>

rn := rn - 4 * 3; ldmia rn, <ra, rb, rc> => ldmdb rn!, <ra, rb, rc>

Definition at line 319 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineBasicBlock::begin(), llvm::ARM_AM::da, llvm::ARM_AM::db, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::ARM_AM::getAM4ModeImm(), llvm::ARM_AM::getAM4SubMode(), llvm::ARM_AM::getAM4WBFlag(), llvm::ARM_AM::getAM5Offset(), llvm::ARM_AM::getAM5Opc(), llvm::ARM_AM::getAM5SubMode(), llvm::ARM_AM::getAM5WBFlag(), llvm::MachineOperand::getImm(), getInstrPredicate(), getLSMultipleTransferSize(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::ARM_AM::ia, llvm::ARM_AM::ib, isMatchingDecrement(), isMatchingIncrement(), MI, llvm::next(), llvm::prior(), and llvm::MachineOperand::setImm().

static bool mergeOps	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		int	Offset,
		unsigned	Base,
		bool	BaseKill,
		int	Opcode,
		ARMCC::CondCodes	Pred,
		unsigned	PredReg,
		unsigned	Scratch,
		SmallVector< std::pair< unsigned, bool >, 8 > &	Regs,
		const TargetInstrInfo *	TII
	)			[static]

mergeOps - Create and insert a LDM or STM with Base as base register and registers in Regs as the register operands that would be loaded / stored. It returns true if the transformation is done.

Definition at line 114 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::ARM_AM::da, llvm::ARM_AM::db, llvm::TargetInstrInfo::get(), llvm::ARM_AM::getAM4ModeImm(), llvm::ARM_AM::getAM5Opc(), getLoadStoreMultipleOpcode(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::ia, and llvm::ARM_AM::ib.

STATISTIC	(	NumFSTMGened	,
		"Number of fstm instructions generated"
	)

STATISTIC	(	NumFLDMGened	,
		"Number of fldm instructions generated"
	)

STATISTIC	(	NumSTMGened	,
		"Number of stm instructions generated"
	)

STATISTIC	(	NumLDMGened	,
		"Number of ldm instructions generated"
	)

---

Variable Documentation

ARMFunctionInfo* AFI

Definition at line 46 of file ARMLoadStoreOptimizer.cpp.

char ID [static]

Definition at line 41 of file ARMLoadStoreOptimizer.cpp.

MachineBasicBlock::iterator MBBI

Definition at line 59 of file ARMLoadStoreOptimizer.cpp.

Referenced by BBHasFallthrough(), llvm::PPCRegisterInfo::eliminateCallFramePseudoInstr(), llvm::XCoreRegisterInfo::emitEpilogue(), llvm::X86RegisterInfo::emitEpilogue(), llvm::SPURegisterInfo::emitEpilogue(), llvm::SparcRegisterInfo::emitEpilogue(), llvm::PPCRegisterInfo::emitEpilogue(), llvm::MipsRegisterInfo::emitEpilogue(), llvm::IA64RegisterInfo::emitEpilogue(), llvm::ARMRegisterInfo::emitEpilogue(), llvm::AlphaRegisterInfo::emitEpilogue(), llvm::XCoreRegisterInfo::emitPrologue(), llvm::X86RegisterInfo::emitPrologue(), llvm::SPURegisterInfo::emitPrologue(), llvm::PPCRegisterInfo::emitPrologue(), llvm::MipsRegisterInfo::emitPrologue(), llvm::IA64RegisterInfo::emitPrologue(), llvm::ARMRegisterInfo::emitPrologue(), llvm::AlphaRegisterInfo::emitPrologue(), llvm::TargetInstrInfoImpl::GetFunctionSizeInBytes(), llvm::X86InstrInfo::getGlobalBaseReg(), llvm::MachineFunction::remove(), RemoveVRSaveCode(), and llvm::MachineFunction::RenumberBlocks().

bool Merged

Definition at line 60 of file ARMLoadStoreOptimizer.cpp.

int Offset

Definition at line 57 of file ARMLoadStoreOptimizer.cpp.

unsigned Position

Definition at line 58 of file ARMLoadStoreOptimizer.cpp.

Referenced by llvm::cl::Option::getPosition(), and llvm::cl::Option::setPosition().

RegScavenger* RS

Definition at line 47 of file ARMLoadStoreOptimizer.cpp.

const TargetInstrInfo* TII

Definition at line 44 of file ARMLoadStoreOptimizer.cpp.

const TargetRegisterInfo* TRI

Definition at line 45 of file ARMLoadStoreOptimizer.cpp.