LLVM API Documentation

IA64InstrInfo.h

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00001 //===- IA64InstrInfo.h - IA64 Instruction Information ----------*- C++ -*- ===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the IA64 implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef IA64INSTRUCTIONINFO_H
00015 #define IA64INSTRUCTIONINFO_H
00016 
00017 #include "llvm/Target/TargetInstrInfo.h"
00018 #include "IA64RegisterInfo.h"
00019 
00020 namespace llvm {
00021 
00022 class IA64InstrInfo : public TargetInstrInfoImpl {
00023   const IA64RegisterInfo RI;
00024 public:
00025   IA64InstrInfo();
00026 
00027   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
00028   /// such, whenever a client has an instance of instruction info, it should
00029   /// always be able to get register info as well (through this method).
00030   ///
00031   virtual const IA64RegisterInfo &getRegisterInfo() const { return RI; }
00032 
00033   /// Return true if the instruction is a register to register move and return
00034   /// the source and dest operands and their sub-register indices by reference.
00035   virtual bool isMoveInstr(const MachineInstr &MI,
00036                            unsigned &SrcReg, unsigned &DstReg,
00037                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
00038   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
00039                                 MachineBasicBlock *FBB,
00040                             const SmallVectorImpl<MachineOperand> &Cond) const;
00041   virtual bool copyRegToReg(MachineBasicBlock &MBB,
00042                             MachineBasicBlock::iterator MI,
00043                             unsigned DestReg, unsigned SrcReg,
00044                             const TargetRegisterClass *DestRC,
00045                             const TargetRegisterClass *SrcRC) const;
00046   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
00047                                    MachineBasicBlock::iterator MI,
00048                                    unsigned SrcReg, bool isKill, int FrameIndex,
00049                                    const TargetRegisterClass *RC) const;
00050 
00051   virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
00052                               SmallVectorImpl<MachineOperand> &Addr,
00053                               const TargetRegisterClass *RC,
00054                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
00055 
00056   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
00057                                     MachineBasicBlock::iterator MI,
00058                                     unsigned DestReg, int FrameIndex,
00059                                     const TargetRegisterClass *RC) const;
00060 
00061   virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
00062                                SmallVectorImpl<MachineOperand> &Addr,
00063                                const TargetRegisterClass *RC,
00064                                SmallVectorImpl<MachineInstr*> &NewMIs) const;
00065 };
00066 
00067 } // End llvm namespace
00068 
00069 #endif
00070