LLVM API Documentation

LLVMTargetMachine.cpp

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00001 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the LLVMTargetMachine class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "llvm/Target/TargetMachine.h"
00015 #include "llvm/PassManager.h"
00016 #include "llvm/Pass.h"
00017 #include "llvm/Assembly/PrintModulePass.h"
00018 #include "llvm/Analysis/LoopPass.h"
00019 #include "llvm/CodeGen/Passes.h"
00020 #include "llvm/CodeGen/GCStrategy.h"
00021 #include "llvm/Target/TargetOptions.h"
00022 #include "llvm/Target/TargetAsmInfo.h"
00023 #include "llvm/Transforms/Scalar.h"
00024 #include "llvm/Support/CommandLine.h"
00025 #include "llvm/Support/raw_ostream.h"
00026 using namespace llvm;
00027 
00028 namespace llvm {
00029   bool EnableFastISel;
00030 }
00031 
00032 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
00033     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
00034 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
00035     cl::desc("Print LLVM IR input to isel pass"));
00036 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
00037     cl::desc("Dump emitter generated instructions as assembly"));
00038 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
00039     cl::desc("Dump garbage collector data"));
00040 
00041 // Hidden options to help debugging
00042 static cl::opt<bool>
00043 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
00044               cl::desc("Perform sinking on machine code"));
00045 static cl::opt<bool>
00046 EnableLICM("machine-licm",
00047            cl::init(false), cl::Hidden,
00048            cl::desc("Perform loop-invariant code motion on machine code"));
00049 
00050 // When this works it will be on by default.
00051 static cl::opt<bool>
00052 DisablePostRAScheduler("disable-post-RA-scheduler",
00053                        cl::desc("Disable scheduling after register allocation"),
00054                        cl::init(true));
00055 
00056 // Enable or disable FastISel. Both options are needed, because
00057 // FastISel is enabled by default with -fast, and we wish to be
00058 // able to enable or disable fast-isel independently from -fast.
00059 static cl::opt<cl::boolOrDefault>
00060 EnableFastISelOption("fast-isel", cl::Hidden,
00061   cl::desc("Enable the experimental \"fast\" instruction selector"));
00062 
00063 FileModel::Model
00064 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
00065                                        raw_ostream &Out,
00066                                        CodeGenFileType FileType,
00067                                        bool Fast) {
00068   // Add common CodeGen passes.
00069   if (addCommonCodeGenPasses(PM, Fast))
00070     return FileModel::Error;
00071 
00072   // Fold redundant debug labels.
00073   PM.add(createDebugLabelFoldingPass());
00074 
00075   if (PrintMachineCode)
00076     PM.add(createMachineFunctionPrinterPass(cerr));
00077 
00078   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
00079     PM.add(createMachineFunctionPrinterPass(cerr));
00080 
00081   if (!Fast)
00082     PM.add(createLoopAlignerPass());
00083 
00084   switch (FileType) {
00085   default:
00086     break;
00087   case TargetMachine::AssemblyFile:
00088     if (addAssemblyEmitter(PM, Fast, Out))
00089       return FileModel::Error;
00090     return FileModel::AsmFile;
00091   case TargetMachine::ObjectFile:
00092     if (getMachOWriterInfo())
00093       return FileModel::MachOFile;
00094     else if (getELFWriterInfo())
00095       return FileModel::ElfFile;
00096   }
00097 
00098   return FileModel::Error;
00099 }
00100 
00101 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
00102 /// be split up (e.g., to add an object writer pass), this method can be used to
00103 /// finish up adding passes to emit the file, if necessary.
00104 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
00105                                                   MachineCodeEmitter *MCE,
00106                                                   bool Fast) {
00107   if (MCE)
00108     addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
00109 
00110   PM.add(createGCInfoDeleter());
00111 
00112   // Delete machine code for this function
00113   PM.add(createMachineCodeDeleter());
00114 
00115   return false; // success!
00116 }
00117 
00118 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
00119 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
00120 /// actually outputting the machine code and resolving things like the address
00121 /// of functions.  This method should returns true if machine code emission is
00122 /// not supported.
00123 ///
00124 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
00125                                                    MachineCodeEmitter &MCE,
00126                                                    bool Fast) {
00127   // Add common CodeGen passes.
00128   if (addCommonCodeGenPasses(PM, Fast))
00129     return true;
00130 
00131   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
00132     PM.add(createMachineFunctionPrinterPass(cerr));
00133 
00134   addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
00135 
00136   PM.add(createGCInfoDeleter());
00137 
00138   // Delete machine code for this function
00139   PM.add(createMachineCodeDeleter());
00140 
00141   return false; // success!
00142 }
00143 
00144 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
00145 /// both emitting to assembly files or machine code output.
00146 ///
00147 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
00148   // Standard LLVM-Level Passes.
00149 
00150   // Run loop strength reduction before anything else.
00151   if (!Fast) {
00152     PM.add(createLoopStrengthReducePass(getTargetLowering()));
00153     if (PrintLSR)
00154       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
00155   }
00156 
00157   PM.add(createGCLoweringPass());
00158 
00159   if (!getTargetAsmInfo()->doesSupportExceptionHandling())
00160     PM.add(createLowerInvokePass(getTargetLowering()));
00161 
00162   // Make sure that no unreachable blocks are instruction selected.
00163   PM.add(createUnreachableBlockEliminationPass());
00164 
00165   if (!Fast)
00166     PM.add(createCodeGenPreparePass(getTargetLowering()));
00167 
00168   PM.add(createStackProtectorPass(getTargetLowering()));
00169 
00170   if (PrintISelInput)
00171     PM.add(createPrintFunctionPass("\n\n"
00172                                    "*** Final LLVM Code input to ISel ***\n",
00173                                    &errs()));
00174 
00175   // Standard Lower-Level Passes.
00176 
00177   // Enable FastISel with -fast, but allow that to be overridden.
00178   if (EnableFastISelOption == cl::BOU_TRUE ||
00179       (Fast && EnableFastISelOption != cl::BOU_FALSE))
00180     EnableFastISel = true;
00181 
00182   // Ask the target for an isel.
00183   if (addInstSelector(PM, Fast))
00184     return true;
00185 
00186   // Print the instruction selected machine code...
00187   if (PrintMachineCode)
00188     PM.add(createMachineFunctionPrinterPass(cerr));
00189 
00190   if (EnableLICM)
00191     PM.add(createMachineLICMPass());
00192 
00193   if (EnableSinking)
00194     PM.add(createMachineSinkingPass());
00195 
00196   // Run pre-ra passes.
00197   if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
00198     PM.add(createMachineFunctionPrinterPass(cerr));
00199 
00200   // Perform register allocation.
00201   PM.add(createRegisterAllocator());
00202 
00203   // Perform stack slot coloring.
00204   if (!Fast)
00205     PM.add(createStackSlotColoringPass());
00206 
00207   if (PrintMachineCode)  // Print the register-allocated code
00208     PM.add(createMachineFunctionPrinterPass(cerr));
00209 
00210   // Run post-ra passes.
00211   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
00212     PM.add(createMachineFunctionPrinterPass(cerr));
00213 
00214   if (PrintMachineCode)
00215     PM.add(createMachineFunctionPrinterPass(cerr));
00216 
00217   PM.add(createLowerSubregsPass());
00218 
00219   if (PrintMachineCode)  // Print the subreg lowered code
00220     PM.add(createMachineFunctionPrinterPass(cerr));
00221 
00222   // Insert prolog/epilog code.  Eliminate abstract frame index references...
00223   PM.add(createPrologEpilogCodeInserter());
00224 
00225   if (PrintMachineCode)
00226     PM.add(createMachineFunctionPrinterPass(cerr));
00227 
00228   // Second pass scheduler.
00229   if (!Fast && !DisablePostRAScheduler) {
00230     PM.add(createPostRAScheduler());
00231 
00232     if (PrintMachineCode)
00233       PM.add(createMachineFunctionPrinterPass(cerr));
00234   }
00235 
00236   // Branch folding must be run after regalloc and prolog/epilog insertion.
00237   if (!Fast)
00238     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
00239 
00240   if (PrintMachineCode)
00241     PM.add(createMachineFunctionPrinterPass(cerr));
00242 
00243   PM.add(createGCMachineCodeAnalysisPass());
00244 
00245   if (PrintMachineCode)
00246     PM.add(createMachineFunctionPrinterPass(cerr));
00247 
00248   if (PrintGCInfo)
00249     PM.add(createGCInfoPrinter(*cerr));
00250 
00251   return false;
00252 }