PPCGenInstrInfo.inc

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//===- TableGen'erated file -------------------------------------*- C++ -*-===//
//
// Target Instruction Descriptors
//
// Automatically generated file, do not edit!
//
//===----------------------------------------------------------------------===//

namespace llvm {

static const unsigned ImplicitList1[] = { PPC::R1, 0 };
static const unsigned ImplicitList2[] = { PPC::CR0, 0 };
static const unsigned ImplicitList3[] = { PPC::CTR, 0 };
static const unsigned ImplicitList4[] = { PPC::CTR8, PPC::RM, 0 };
static const TargetRegisterClass* Barriers1[] = { &PPC::CTRRC8RegClass, NULL };
static const unsigned ImplicitList5[] = { PPC::X0, PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
static const unsigned ImplicitList6[] = { PPC::CTR, PPC::RM, 0 };
static const TargetRegisterClass* Barriers2[] = { &PPC::CTRRCRegClass, NULL };
static const unsigned ImplicitList7[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, 0 };
static const unsigned ImplicitList8[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, 0 };
static const unsigned ImplicitList9[] = { PPC::RM, 0 };
static const unsigned ImplicitList10[] = { PPC::LR, PPC::RM, 0 };
static const unsigned ImplicitList11[] = { PPC::X1, 0 };
static const unsigned ImplicitList12[] = { PPC::CTR8, 0 };
static const unsigned ImplicitList13[] = { PPC::LR, 0 };
static const unsigned ImplicitList14[] = { PPC::LR8, 0 };
static const unsigned ImplicitList15[] = { PPC::CR6, 0 };

static const TargetOperandInfo OperandInfo2[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo3[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo4[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo5[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo6[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo7[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo8[] = { { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo9[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo10[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo11[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo12[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo13[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo14[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { PPC::CRRCRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo15[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { PPC::CRRCRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo16[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo17[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo18[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo19[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo20[] = { { PPC::CRBITRCRegClassID, 0, 0 }, { PPC::CRBITRCRegClassID, 0, 0 }, { PPC::CRBITRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo21[] = { { PPC::CRBITRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo22[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo23[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo24[] = { { 0, 0, 0 }, { 0, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo25[] = { { 0, 0, 0 }, { 0, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo26[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo27[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo28[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo29[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo30[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo31[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo32[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo33[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo34[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo35[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo36[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo37[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo38[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo39[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo40[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo41[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo42[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo43[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo44[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo45[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo46[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo47[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo48[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo49[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo50[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo51[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo52[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo53[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo54[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo55[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo56[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo57[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo58[] = { { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo59[] = { { PPC::G8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo60[] = { { PPC::F8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo61[] = { { PPC::VRRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo62[] = { { 0, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo63[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo64[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo65[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo66[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo67[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo68[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo69[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo70[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo71[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo72[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo73[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo74[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo75[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo76[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo77[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo78[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo79[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo80[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo81[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo82[] = { { PPC::CTRRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo83[] = { { PPC::CTRRC8RegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo84[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo85[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo86[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo87[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo88[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo89[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, };

static const TargetInstrDesc PPCInsts[] = {
  { 0,  0,  0,  52, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 },  // Inst #0 = PHI
  { 1,  0,  0,  52, "INLINEASM", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 },  // Inst #1 = INLINEASM
  { 2,  1,  0,  52, "DBG_LABEL", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo8 },  // Inst #2 = DBG_LABEL
  { 3,  1,  0,  52, "EH_LABEL", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo8 },  // Inst #3 = EH_LABEL
  { 4,  1,  0,  52, "GC_LABEL", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo8 },  // Inst #4 = GC_LABEL
  { 5,  0,  0,  52, "DECLARE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 },  // Inst #5 = DECLARE
  { 6,  3,  1,  52, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo26 },  // Inst #6 = EXTRACT_SUBREG
  { 7,  4,  1,  52, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo41 },  // Inst #7 = INSERT_SUBREG
  { 8,  1,  1,  52, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo8 },  // Inst #8 = IMPLICIT_DEF
  { 9,  4,  1,  52, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo23 },  // Inst #9 = SUBREG_TO_REG
  { 10, 3,  1,  14, "ADD4", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #10 = ADD4
  { 11, 3,  1,  14, "ADD8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #11 = ADD8
  { 12, 3,  1,  14, "ADDC", 0, 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #12 = ADDC
  { 13, 3,  1,  14, "ADDC8", 0, 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #13 = ADDC8
  { 14, 3,  1,  14, "ADDE", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #14 = ADDE
  { 15, 3,  1,  14, "ADDE8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #15 = ADDE8
  { 16, 3,  1,  14, "ADDI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #16 = ADDI
  { 17, 3,  1,  14, "ADDI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 },  // Inst #17 = ADDI8
  { 18, 3,  1,  14, "ADDIC", 0, 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #18 = ADDIC
  { 19, 3,  1,  14, "ADDICo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #19 = ADDICo
  { 20, 3,  1,  14, "ADDIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #20 = ADDIS
  { 21, 3,  1,  14, "ADDIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 },  // Inst #21 = ADDIS8
  { 22, 2,  1,  14, "ADDME", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 },  // Inst #22 = ADDME
  { 23, 2,  1,  14, "ADDME8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 },  // Inst #23 = ADDME8
  { 24, 2,  1,  14, "ADDZE", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 },  // Inst #24 = ADDZE
  { 25, 2,  1,  14, "ADDZE8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 },  // Inst #25 = ADDZE8
  { 26, 1,  0,  52, "ADJCALLSTACKDOWN", 0, 0, ImplicitList1, ImplicitList1, NULL, OperandInfo8 },  // Inst #26 = ADJCALLSTACKDOWN
  { 27, 2,  0,  52, "ADJCALLSTACKUP", 0, 0, ImplicitList1, ImplicitList1, NULL, OperandInfo9 },  // Inst #27 = ADJCALLSTACKUP
  { 28, 3,  1,  14, "AND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #28 = AND
  { 29, 3,  1,  14, "AND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #29 = AND8
  { 30, 3,  1,  14, "ANDC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #30 = ANDC
  { 31, 3,  1,  14, "ANDC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #31 = ANDC8
  { 32, 3,  1,  14, "ANDISo", 0, 0|(1<<3), NULL, ImplicitList2, NULL, OperandInfo4 },  // Inst #32 = ANDISo
  { 33, 3,  1,  14, "ANDISo8", 0, 0|(1<<3), NULL, ImplicitList2, NULL, OperandInfo5 },  // Inst #33 = ANDISo8
  { 34, 3,  1,  14, "ANDIo", 0, 0|(1<<3), NULL, ImplicitList2, NULL, OperandInfo4 },  // Inst #34 = ANDIo
  { 35, 3,  1,  14, "ANDIo8", 0, 0|(1<<3), NULL, ImplicitList2, NULL, OperandInfo5 },  // Inst #35 = ANDIo8
  { 36, 5,  1,  52, "ATOMIC_CMP_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo10 },  // Inst #36 = ATOMIC_CMP_SWAP_I16
  { 37, 5,  1,  52, "ATOMIC_CMP_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo10 },  // Inst #37 = ATOMIC_CMP_SWAP_I32
  { 38, 5,  1,  52, "ATOMIC_CMP_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo11 },  // Inst #38 = ATOMIC_CMP_SWAP_I64
  { 39, 5,  1,  52, "ATOMIC_CMP_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo10 },  // Inst #39 = ATOMIC_CMP_SWAP_I8
  { 40, 4,  1,  52, "ATOMIC_LOAD_ADD_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #40 = ATOMIC_LOAD_ADD_I16
  { 41, 4,  1,  52, "ATOMIC_LOAD_ADD_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #41 = ATOMIC_LOAD_ADD_I32
  { 42, 4,  1,  52, "ATOMIC_LOAD_ADD_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo13 },  // Inst #42 = ATOMIC_LOAD_ADD_I64
  { 43, 4,  1,  52, "ATOMIC_LOAD_ADD_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #43 = ATOMIC_LOAD_ADD_I8
  { 44, 4,  1,  52, "ATOMIC_LOAD_AND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #44 = ATOMIC_LOAD_AND_I16
  { 45, 4,  1,  52, "ATOMIC_LOAD_AND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #45 = ATOMIC_LOAD_AND_I32
  { 46, 4,  1,  52, "ATOMIC_LOAD_AND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo13 },  // Inst #46 = ATOMIC_LOAD_AND_I64
  { 47, 4,  1,  52, "ATOMIC_LOAD_AND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #47 = ATOMIC_LOAD_AND_I8
  { 48, 4,  1,  52, "ATOMIC_LOAD_NAND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #48 = ATOMIC_LOAD_NAND_I16
  { 49, 4,  1,  52, "ATOMIC_LOAD_NAND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #49 = ATOMIC_LOAD_NAND_I32
  { 50, 4,  1,  52, "ATOMIC_LOAD_NAND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo13 },  // Inst #50 = ATOMIC_LOAD_NAND_I64
  { 51, 4,  1,  52, "ATOMIC_LOAD_NAND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #51 = ATOMIC_LOAD_NAND_I8
  { 52, 4,  1,  52, "ATOMIC_LOAD_OR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #52 = ATOMIC_LOAD_OR_I16
  { 53, 4,  1,  52, "ATOMIC_LOAD_OR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #53 = ATOMIC_LOAD_OR_I32
  { 54, 4,  1,  52, "ATOMIC_LOAD_OR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo13 },  // Inst #54 = ATOMIC_LOAD_OR_I64
  { 55, 4,  1,  52, "ATOMIC_LOAD_OR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #55 = ATOMIC_LOAD_OR_I8
  { 56, 4,  1,  52, "ATOMIC_LOAD_SUB_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #56 = ATOMIC_LOAD_SUB_I16
  { 57, 4,  1,  52, "ATOMIC_LOAD_SUB_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #57 = ATOMIC_LOAD_SUB_I32
  { 58, 4,  1,  52, "ATOMIC_LOAD_SUB_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo13 },  // Inst #58 = ATOMIC_LOAD_SUB_I64
  { 59, 4,  1,  52, "ATOMIC_LOAD_SUB_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #59 = ATOMIC_LOAD_SUB_I8
  { 60, 4,  1,  52, "ATOMIC_LOAD_XOR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #60 = ATOMIC_LOAD_XOR_I16
  { 61, 4,  1,  52, "ATOMIC_LOAD_XOR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #61 = ATOMIC_LOAD_XOR_I32
  { 62, 4,  1,  52, "ATOMIC_LOAD_XOR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo13 },  // Inst #62 = ATOMIC_LOAD_XOR_I64
  { 63, 4,  1,  52, "ATOMIC_LOAD_XOR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #63 = ATOMIC_LOAD_XOR_I8
  { 64, 4,  1,  52, "ATOMIC_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #64 = ATOMIC_SWAP_I16
  { 65, 4,  1,  52, "ATOMIC_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #65 = ATOMIC_SWAP_I32
  { 66, 4,  1,  52, "ATOMIC_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo13 },  // Inst #66 = ATOMIC_SWAP_I64
  { 67, 4,  1,  52, "ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomDAGSchedInserter), 0, ImplicitList2, NULL, NULL, OperandInfo12 },  // Inst #67 = ATOMIC_SWAP_I8
  { 68, 1,  0,  0,  "B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(7<<3), NULL, NULL, NULL, OperandInfo8 },  // Inst #68 = B
  { 69, 3,  0,  0,  "BCC", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, NULL, NULL, OperandInfo14 },  // Inst #69 = BCC
  { 70, 0,  0,  0,  "BCTR", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList3, NULL, NULL, 0 },  // Inst #70 = BCTR
  { 71, 0,  0,  0,  "BCTRL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList4, ImplicitList5, Barriers1, 0 },  // Inst #71 = BCTRL8_ELF
  { 72, 0,  0,  0,  "BCTRL8_Macho", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList4, ImplicitList5, Barriers1, 0 },  // Inst #72 = BCTRL8_Macho
  { 73, 0,  0,  0,  "BCTRL_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList6, ImplicitList7, Barriers2, 0 },  // Inst #73 = BCTRL_ELF
  { 74, 0,  0,  0,  "BCTRL_Macho", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList6, ImplicitList8, Barriers2, 0 },  // Inst #74 = BCTRL_Macho
  { 75, 1,  0,  0,  "BL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList9, ImplicitList5, Barriers1, OperandInfo8 },  // Inst #75 = BL8_ELF
  { 76, 1,  0,  0,  "BL8_Macho", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList9, ImplicitList5, Barriers1, OperandInfo8 },  // Inst #76 = BL8_Macho
  { 77, 1,  0,  0,  "BLA8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList9, ImplicitList5, Barriers1, OperandInfo8 },  // Inst #77 = BLA8_ELF
  { 78, 1,  0,  0,  "BLA8_Macho", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList9, ImplicitList5, Barriers1, OperandInfo8 },  // Inst #78 = BLA8_Macho
  { 79, 1,  0,  0,  "BLA_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList9, ImplicitList7, Barriers2, OperandInfo8 },  // Inst #79 = BLA_ELF
  { 80, 1,  0,  0,  "BLA_Macho", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList9, ImplicitList8, Barriers2, OperandInfo8 },  // Inst #80 = BLA_Macho
  { 81, 2,  0,  0,  "BLR", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo15 },  // Inst #81 = BLR
  { 82, 1,  0,  0,  "BL_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList9, ImplicitList7, Barriers2, OperandInfo8 },  // Inst #82 = BL_ELF
  { 83, 1,  0,  0,  "BL_Macho", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList9, ImplicitList8, Barriers2, OperandInfo8 },  // Inst #83 = BL_Macho
  { 84, 3,  1,  11, "CMPD", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo16 },  // Inst #84 = CMPD
  { 85, 3,  1,  11, "CMPDI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo17 },  // Inst #85 = CMPDI
  { 86, 3,  1,  11, "CMPLD", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo16 },  // Inst #86 = CMPLD
  { 87, 3,  1,  11, "CMPLDI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo17 },  // Inst #87 = CMPLDI
  { 88, 3,  1,  11, "CMPLW", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo18 },  // Inst #88 = CMPLW
  { 89, 3,  1,  11, "CMPLWI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo19 },  // Inst #89 = CMPLWI
  { 90, 3,  1,  11, "CMPW", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo18 },  // Inst #90 = CMPW
  { 91, 3,  1,  11, "CMPWI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo19 },  // Inst #91 = CMPWI
  { 92, 2,  1,  14, "CNTLZD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 },  // Inst #92 = CNTLZD
  { 93, 2,  1,  14, "CNTLZW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 },  // Inst #93 = CNTLZW
  { 94, 3,  1,  1,  "CREQV", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo20 },  // Inst #94 = CREQV
  { 95, 3,  1,  1,  "CROR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo20 },  // Inst #95 = CROR
  { 96, 1,  1,  1,  "CRSET", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo21 },  // Inst #96 = CRSET
  { 97, 2,  0,  30, "DCBA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo22 },  // Inst #97 = DCBA
  { 98, 2,  0,  30, "DCBF", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo22 },  // Inst #98 = DCBF
  { 99, 2,  0,  30, "DCBI", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo22 },  // Inst #99 = DCBI
  { 100,  2,  0,  30, "DCBST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo22 },  // Inst #100 = DCBST
  { 101,  2,  0,  30, "DCBT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo22 },  // Inst #101 = DCBT
  { 102,  2,  0,  30, "DCBTST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo22 },  // Inst #102 = DCBTST
  { 103,  2,  0,  30, "DCBZ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo22 },  // Inst #103 = DCBZ
  { 104,  2,  0,  30, "DCBZL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo22 },  // Inst #104 = DCBZL
  { 105,  3,  1,  12, "DIVD", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #105 = DIVD
  { 106,  3,  1,  12, "DIVDU", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #106 = DIVDU
  { 107,  3,  1,  13, "DIVW", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #107 = DIVW
  { 108,  3,  1,  13, "DIVWU", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #108 = DIVWU
  { 109,  4,  0,  33, "DSS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo23 },  // Inst #109 = DSS
  { 110,  4,  0,  33, "DSSALL", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo23 },  // Inst #110 = DSSALL
  { 111,  4,  0,  33, "DST", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 },  // Inst #111 = DST
  { 112,  4,  0,  33, "DST64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 },  // Inst #112 = DST64
  { 113,  4,  0,  33, "DSTST", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 },  // Inst #113 = DSTST
  { 114,  4,  0,  33, "DSTST64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 },  // Inst #114 = DSTST64
  { 115,  4,  0,  33, "DSTSTT", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 },  // Inst #115 = DSTSTT
  { 116,  4,  0,  33, "DSTSTT64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 },  // Inst #116 = DSTSTT64
  { 117,  4,  0,  33, "DSTT", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 },  // Inst #117 = DSTT
  { 118,  4,  0,  33, "DSTT64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 },  // Inst #118 = DSTT64
  { 119,  3,  0,  52, "DWARF_LOC", 0, 0, NULL, NULL, NULL, OperandInfo26 },  // Inst #119 = DWARF_LOC
  { 120,  4,  1,  52, "DYNALLOC", 0, 0, ImplicitList1, ImplicitList1, NULL, OperandInfo27 },  // Inst #120 = DYNALLOC
  { 121,  4,  1,  52, "DYNALLOC8", 0, 0, ImplicitList11, ImplicitList11, NULL, OperandInfo28 },  // Inst #121 = DYNALLOC8
  { 122,  3,  1,  14, "EQV", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #122 = EQV
  { 123,  3,  1,  14, "EQV8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #123 = EQV8
  { 124,  2,  1,  14, "EXTSB", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 },  // Inst #124 = EXTSB
  { 125,  2,  1,  14, "EXTSB8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 },  // Inst #125 = EXTSB8
  { 126,  2,  1,  14, "EXTSH", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 },  // Inst #126 = EXTSH
  { 127,  2,  1,  14, "EXTSH8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 },  // Inst #127 = EXTSH8
  { 128,  2,  1,  14, "EXTSW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 },  // Inst #128 = EXTSW
  { 129,  2,  1,  14, "EXTSW_32", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 },  // Inst #129 = EXTSW_32
  { 130,  2,  1,  14, "EXTSW_32_64", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo29 },  // Inst #130 = EXTSW_32_64
  { 131,  2,  1,  8,  "FABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 },  // Inst #131 = FABSD
  { 132,  2,  1,  8,  "FABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 },  // Inst #132 = FABSS
  { 133,  3,  1,  8,  "FADD", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo32 },  // Inst #133 = FADD
  { 134,  3,  1,  8,  "FADDS", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo33 },  // Inst #134 = FADDS
  { 135,  3,  1,  8,  "FADDrtz", 0, 0|(1<<1)|(3<<3), ImplicitList9, NULL, NULL, OperandInfo32 },  // Inst #135 = FADDrtz
  { 136,  2,  1,  8,  "FCFID", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo30 },  // Inst #136 = FCFID
  { 137,  3,  1,  4,  "FCMPUD", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<3), NULL, NULL, NULL, OperandInfo34 },  // Inst #137 = FCMPUD
  { 138,  3,  1,  4,  "FCMPUS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<3), NULL, NULL, NULL, OperandInfo35 },  // Inst #138 = FCMPUS
  { 139,  2,  1,  8,  "FCTIDZ", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo30 },  // Inst #139 = FCTIDZ
  { 140,  2,  1,  8,  "FCTIWZ", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo30 },  // Inst #140 = FCTIWZ
  { 141,  3,  1,  5,  "FDIV", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo32 },  // Inst #141 = FDIV
  { 142,  3,  1,  6,  "FDIVS", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo33 },  // Inst #142 = FDIVS
  { 143,  4,  1,  7,  "FMADD", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo36 },  // Inst #143 = FMADD
  { 144,  4,  1,  8,  "FMADDS", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo37 },  // Inst #144 = FMADDS
  { 145,  2,  1,  8,  "FMRD", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo30 },  // Inst #145 = FMRD
  { 146,  2,  1,  8,  "FMRS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo31 },  // Inst #146 = FMRS
  { 147,  2,  1,  8,  "FMRSD", 0, 0, NULL, NULL, NULL, OperandInfo38 },  // Inst #147 = FMRSD
  { 148,  4,  1,  7,  "FMSUB", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo36 },  // Inst #148 = FMSUB
  { 149,  4,  1,  8,  "FMSUBS", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo37 },  // Inst #149 = FMSUBS
  { 150,  3,  1,  7,  "FMUL", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo32 },  // Inst #150 = FMUL
  { 151,  3,  1,  8,  "FMULS", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo33 },  // Inst #151 = FMULS
  { 152,  2,  1,  8,  "FNABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 },  // Inst #152 = FNABSD
  { 153,  2,  1,  8,  "FNABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 },  // Inst #153 = FNABSS
  { 154,  2,  1,  8,  "FNEGD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 },  // Inst #154 = FNEGD
  { 155,  2,  1,  8,  "FNEGS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 },  // Inst #155 = FNEGS
  { 156,  4,  1,  7,  "FNMADD", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo36 },  // Inst #156 = FNMADD
  { 157,  4,  1,  8,  "FNMADDS", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo37 },  // Inst #157 = FNMADDS
  { 158,  4,  1,  7,  "FNMSUB", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo36 },  // Inst #158 = FNMSUB
  { 159,  4,  1,  8,  "FNMSUBS", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo37 },  // Inst #159 = FNMSUBS
  { 160,  2,  1,  8,  "FRSP", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo39 },  // Inst #160 = FRSP
  { 161,  4,  1,  8,  "FSELD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo36 },  // Inst #161 = FSELD
  { 162,  4,  1,  8,  "FSELS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo40 },  // Inst #162 = FSELS
  { 163,  2,  1,  10, "FSQRT", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo30 },  // Inst #163 = FSQRT
  { 164,  2,  1,  10, "FSQRTS", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo31 },  // Inst #164 = FSQRTS
  { 165,  3,  1,  8,  "FSUB", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo32 },  // Inst #165 = FSUB
  { 166,  3,  1,  8,  "FSUBS", 0, 0|(3<<3), ImplicitList9, NULL, NULL, OperandInfo33 },  // Inst #166 = FSUBS
  { 167,  3,  1,  14, "LA", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #167 = LA
  { 168,  3,  1,  33, "LBZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 },  // Inst #168 = LBZ
  { 169,  3,  1,  33, "LBZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 },  // Inst #169 = LBZ8
  { 170,  4,  2,  33, "LBZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 },  // Inst #170 = LBZU
  { 171,  4,  2,  33, "LBZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 },  // Inst #171 = LBZU8
  { 172,  3,  1,  33, "LBZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #172 = LBZX
  { 173,  3,  1,  33, "LBZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #173 = LBZX8
  { 174,  3,  1,  35, "LD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 },  // Inst #174 = LD
  { 175,  3,  1,  36, "LDARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo47 },  // Inst #175 = LDARX
  { 176,  4,  2,  35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 },  // Inst #176 = LDU
  { 177,  3,  1,  35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #177 = LDX
  { 178,  3,  1,  37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 },  // Inst #178 = LFD
  { 179,  4,  2,  37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 },  // Inst #179 = LFDU
  { 180,  3,  1,  38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 },  // Inst #180 = LFDX
  { 181,  3,  1,  38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 },  // Inst #181 = LFS
  { 182,  4,  2,  38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 },  // Inst #182 = LFSU
  { 183,  3,  1,  38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 },  // Inst #183 = LFSX
  { 184,  3,  1,  39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 },  // Inst #184 = LHA
  { 185,  3,  1,  39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 },  // Inst #185 = LHA8
  { 186,  4,  2,  33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 },  // Inst #186 = LHAU
  { 187,  4,  2,  33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 },  // Inst #187 = LHAU8
  { 188,  3,  1,  39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #188 = LHAX
  { 189,  3,  1,  39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #189 = LHAX8
  { 190,  3,  1,  33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #190 = LHBRX
  { 191,  3,  1,  33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 },  // Inst #191 = LHZ
  { 192,  3,  1,  33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 },  // Inst #192 = LHZ8
  { 193,  4,  2,  33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 },  // Inst #193 = LHZU
  { 194,  4,  2,  33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 },  // Inst #194 = LHZU8
  { 195,  3,  1,  33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #195 = LHZX
  { 196,  3,  1,  33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #196 = LHZX8
  { 197,  2,  1,  14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo54 },  // Inst #197 = LI
  { 198,  2,  1,  14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo55 },  // Inst #198 = LI8
  { 199,  2,  1,  14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo54 },  // Inst #199 = LIS
  { 200,  2,  1,  14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo55 },  // Inst #200 = LIS8
  { 201,  3,  1,  33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #201 = LVEBX
  { 202,  3,  1,  33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #202 = LVEHX
  { 203,  3,  1,  33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #203 = LVEWX
  { 204,  3,  1,  33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #204 = LVSL
  { 205,  3,  1,  33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #205 = LVSR
  { 206,  3,  1,  33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #206 = LVX
  { 207,  3,  1,  33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #207 = LVXL
  { 208,  3,  1,  42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 },  // Inst #208 = LWA
  { 209,  3,  1,  43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 },  // Inst #209 = LWARX
  { 210,  3,  1,  39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #210 = LWAX
  { 211,  3,  1,  33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #211 = LWBRX
  { 212,  3,  1,  33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 },  // Inst #212 = LWZ
  { 213,  3,  1,  33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 },  // Inst #213 = LWZ8
  { 214,  4,  2,  33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 },  // Inst #214 = LWZU
  { 215,  4,  2,  33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 },  // Inst #215 = LWZU8
  { 216,  3,  1,  33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #216 = LWZX
  { 217,  3,  1,  33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #217 = LWZX8
  { 218,  2,  1,  2,  "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo57 },  // Inst #218 = MCRF
  { 219,  1,  1,  54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo58 },  // Inst #219 = MFCR
  { 220,  1,  1,  56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList3, NULL, NULL, OperandInfo58 },  // Inst #220 = MFCTR
  { 221,  1,  1,  56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList12, NULL, NULL, OperandInfo59 },  // Inst #221 = MFCTR8
  { 222,  1,  1,  15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList9, NULL, NULL, OperandInfo60 },  // Inst #222 = MFFS
  { 223,  1,  1,  56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo58 },  // Inst #223 = MFLR
  { 224,  1,  1,  56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo59 },  // Inst #224 = MFLR8
  { 225,  2,  1,  54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo54 },  // Inst #225 = MFOCRF
  { 226,  1,  1,  14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo58 },  // Inst #226 = MFVRSAVE
  { 227,  1,  1,  33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo61 },  // Inst #227 = MFVSCR
  { 228,  2,  0,  3,  "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo62 },  // Inst #228 = MTCRF
  { 229,  1,  0,  60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList3, Barriers2, OperandInfo58 },  // Inst #229 = MTCTR
  { 230,  1,  0,  60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList12, Barriers1, OperandInfo59 },  // Inst #230 = MTCTR8
  { 231,  1,  0,  17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList9, ImplicitList9, NULL, OperandInfo8 },  // Inst #231 = MTFSB0
  { 232,  1,  0,  17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList9, ImplicitList9, NULL, OperandInfo8 },  // Inst #232 = MTFSB1
  { 233,  4,  1,  17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList9, ImplicitList9, NULL, OperandInfo63 },  // Inst #233 = MTFSF
  { 234,  1,  0,  60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList13, NULL, OperandInfo58 },  // Inst #234 = MTLR
  { 235,  1,  0,  60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo59 },  // Inst #235 = MTLR8
  { 236,  1,  0,  14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo58 },  // Inst #236 = MTVRSAVE
  { 237,  1,  0,  33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo61 },  // Inst #237 = MTVSCR
  { 238,  3,  1,  20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #238 = MULHD
  { 239,  3,  1,  21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #239 = MULHDU
  { 240,  3,  1,  20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #240 = MULHW
  { 241,  3,  1,  21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #241 = MULHWU
  { 242,  3,  1,  19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #242 = MULLD
  { 243,  3,  1,  22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #243 = MULLI
  { 244,  3,  1,  20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #244 = MULLW
  { 245,  1,  0,  52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList13, NULL, OperandInfo8 },  // Inst #245 = MovePCtoLR
  { 246,  1,  0,  52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 },  // Inst #246 = MovePCtoLR8
  { 247,  3,  1,  14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #247 = NAND
  { 248,  3,  1,  14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #248 = NAND8
  { 249,  2,  1,  14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 },  // Inst #249 = NEG
  { 250,  2,  1,  14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 },  // Inst #250 = NEG8
  { 251,  0,  0,  14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 },  // Inst #251 = NOP
  { 252,  3,  1,  14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #252 = NOR
  { 253,  3,  1,  14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #253 = NOR8
  { 254,  3,  1,  14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #254 = OR
  { 255,  3,  1,  14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo64 },  // Inst #255 = OR4To8
  { 256,  3,  1,  14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #256 = OR8
  { 257,  3,  1,  14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 },  // Inst #257 = OR8To4
  { 258,  3,  1,  14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #258 = ORC
  { 259,  3,  1,  14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #259 = ORC8
  { 260,  3,  1,  14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #260 = ORI
  { 261,  3,  1,  14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 },  // Inst #261 = ORI8
  { 262,  3,  1,  14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #262 = ORIS
  { 263,  3,  1,  14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 },  // Inst #263 = ORIS8
  { 264,  4,  1,  25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 },  // Inst #264 = RLDCL
  { 265,  4,  1,  25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 },  // Inst #265 = RLDICL
  { 266,  4,  1,  25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 },  // Inst #266 = RLDICR
  { 267,  5,  1,  25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 },  // Inst #267 = RLDIMI
  { 268,  6,  1,  24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo69 },  // Inst #268 = RLWIMI
  { 269,  5,  1,  14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo70 },  // Inst #269 = RLWINM
  { 270,  5,  1,  14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList2, NULL, OperandInfo70 },  // Inst #270 = RLWINMo
  { 271,  5,  1,  14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 },  // Inst #271 = RLWNM
  { 272,  5,  1,  52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomDAGSchedInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo72 },  // Inst #272 = SELECT_CC_F4
  { 273,  5,  1,  52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomDAGSchedInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 },  // Inst #273 = SELECT_CC_F8
  { 274,  5,  1,  52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomDAGSchedInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 },  // Inst #274 = SELECT_CC_I4
  { 275,  5,  1,  52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomDAGSchedInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 },  // Inst #275 = SELECT_CC_I8
  { 276,  5,  1,  52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomDAGSchedInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 },  // Inst #276 = SELECT_CC_VRRC
  { 277,  3,  1,  25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo77 },  // Inst #277 = SLD
  { 278,  3,  1,  14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #278 = SLW
  { 279,  3,  0,  52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 },  // Inst #279 = SPILL_CR
  { 280,  3,  1,  25, "SRAD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo77 },  // Inst #280 = SRAD
  { 281,  3,  1,  25, "SRADI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 },  // Inst #281 = SRADI
  { 282,  3,  1,  26, "SRAW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #282 = SRAW
  { 283,  3,  1,  26, "SRAWI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #283 = SRAWI
  { 284,  3,  1,  25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo77 },  // Inst #284 = SRD
  { 285,  3,  1,  14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #285 = SRW
  { 286,  3,  0,  33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 },  // Inst #286 = STB
  { 287,  3,  0,  33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 },  // Inst #287 = STB8
  { 288,  4,  1,  33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo78 },  // Inst #288 = STBU
  { 289,  4,  1,  33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 },  // Inst #289 = STBU8
  { 290,  3,  0,  33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #290 = STBX
  { 291,  3,  0,  33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #291 = STBX8
  { 292,  3,  0,  46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 },  // Inst #292 = STD
  { 293,  3,  0,  47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList2, NULL, OperandInfo47 },  // Inst #293 = STDCX
  { 294,  4,  1,  46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 },  // Inst #294 = STDU
  { 295,  3,  0,  46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #295 = STDUX
  { 296,  3,  0,  46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #296 = STDX
  { 297,  3,  0,  46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #297 = STDX_32
  { 298,  3,  0,  46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 },  // Inst #298 = STD_32
  { 299,  3,  0,  51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 },  // Inst #299 = STFD
  { 300,  4,  1,  33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 },  // Inst #300 = STFDU
  { 301,  3,  0,  51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 },  // Inst #301 = STFDX
  { 302,  3,  0,  51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 },  // Inst #302 = STFIWX
  { 303,  3,  0,  51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 },  // Inst #303 = STFS
  { 304,  4,  1,  33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 },  // Inst #304 = STFSU
  { 305,  3,  0,  51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 },  // Inst #305 = STFSX
  { 306,  3,  0,  33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 },  // Inst #306 = STH
  { 307,  3,  0,  33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 },  // Inst #307 = STH8
  { 308,  3,  0,  33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #308 = STHBRX
  { 309,  4,  1,  33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo78 },  // Inst #309 = STHU
  { 310,  4,  1,  33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 },  // Inst #310 = STHU8
  { 311,  3,  0,  33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #311 = STHX
  { 312,  3,  0,  33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #312 = STHX8
  { 313,  3,  0,  33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #313 = STVEBX
  { 314,  3,  0,  33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #314 = STVEHX
  { 315,  3,  0,  33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #315 = STVEWX
  { 316,  3,  0,  33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #316 = STVX
  { 317,  3,  0,  33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo56 },  // Inst #317 = STVXL
  { 318,  3,  0,  33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 },  // Inst #318 = STW
  { 319,  3,  0,  33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 },  // Inst #319 = STW8
  { 320,  3,  0,  33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #320 = STWBRX
  { 321,  3,  0,  49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList2, NULL, OperandInfo46 },  // Inst #321 = STWCX
  { 322,  4,  1,  33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo78 },  // Inst #322 = STWU
  { 323,  4,  1,  33, "STWU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 },  // Inst #323 = STWU8
  { 324,  3,  0,  33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #324 = STWUX
  { 325,  3,  0,  33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 },  // Inst #325 = STWX
  { 326,  3,  0,  33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 },  // Inst #326 = STWX8
  { 327,  3,  1,  14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #327 = SUBF
  { 328,  3,  1,  14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #328 = SUBF8
  { 329,  3,  1,  14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #329 = SUBFC
  { 330,  3,  1,  14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #330 = SUBFC8
  { 331,  3,  1,  14, "SUBFE", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #331 = SUBFE
  { 332,  3,  1,  14, "SUBFE8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #332 = SUBFE8
  { 333,  3,  1,  14, "SUBFIC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #333 = SUBFIC
  { 334,  3,  1,  14, "SUBFIC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 },  // Inst #334 = SUBFIC8
  { 335,  2,  1,  14, "SUBFME", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 },  // Inst #335 = SUBFME
  { 336,  2,  1,  14, "SUBFME8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 },  // Inst #336 = SUBFME8
  { 337,  2,  1,  14, "SUBFZE", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 },  // Inst #337 = SUBFZE
  { 338,  2,  1,  14, "SUBFZE8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 },  // Inst #338 = SUBFZE8
  { 339,  0,  0,  50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 },  // Inst #339 = SYNC
  { 340,  1,  0,  0,  "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList9, NULL, NULL, OperandInfo8 },  // Inst #340 = TAILB
  { 341,  1,  0,  0,  "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList9, NULL, NULL, OperandInfo8 },  // Inst #341 = TAILB8
  { 342,  1,  0,  0,  "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList9, NULL, NULL, OperandInfo8 },  // Inst #342 = TAILBA
  { 343,  1,  0,  0,  "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList9, NULL, NULL, OperandInfo8 },  // Inst #343 = TAILBA8
  { 344,  0,  0,  0,  "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList6, NULL, NULL, 0 },  // Inst #344 = TAILBCTR
  { 345,  0,  0,  0,  "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList6, NULL, NULL, 0 },  // Inst #345 = TAILBCTR8
  { 346,  2,  0,  52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList9, NULL, NULL, OperandInfo9 },  // Inst #346 = TCRETURNai
  { 347,  2,  0,  52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList9, NULL, NULL, OperandInfo9 },  // Inst #347 = TCRETURNai8
  { 348,  2,  0,  52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList9, NULL, NULL, OperandInfo9 },  // Inst #348 = TCRETURNdi
  { 349,  2,  0,  52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList9, NULL, NULL, OperandInfo9 },  // Inst #349 = TCRETURNdi8
  { 350,  2,  0,  52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList9, NULL, NULL, OperandInfo82 },  // Inst #350 = TCRETURNri
  { 351,  2,  0,  52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList9, NULL, NULL, OperandInfo83 },  // Inst #351 = TCRETURNri8
  { 352,  0,  0,  33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 },  // Inst #352 = TRAP
  { 353,  2,  1,  52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 },  // Inst #353 = UPDATE_VRSAVE
  { 354,  3,  1,  67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #354 = VADDCUW
  { 355,  3,  1,  67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #355 = VADDFP
  { 356,  3,  1,  67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #356 = VADDSBS
  { 357,  3,  1,  67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #357 = VADDSHS
  { 358,  3,  1,  67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #358 = VADDSWS
  { 359,  3,  1,  70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #359 = VADDUBM
  { 360,  3,  1,  67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #360 = VADDUBS
  { 361,  3,  1,  70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #361 = VADDUHM
  { 362,  3,  1,  67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #362 = VADDUHS
  { 363,  3,  1,  70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #363 = VADDUWM
  { 364,  3,  1,  67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #364 = VADDUWS
  { 365,  3,  1,  67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #365 = VAND
  { 366,  3,  1,  67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #366 = VANDC
  { 367,  3,  1,  67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #367 = VAVGSB
  { 368,  3,  1,  67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #368 = VAVGSH
  { 369,  3,  1,  67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #369 = VAVGSW
  { 370,  3,  1,  67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #370 = VAVGUB
  { 371,  3,  1,  67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #371 = VAVGUH
  { 372,  3,  1,  67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #372 = VAVGUW
  { 373,  3,  1,  67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 },  // Inst #373 = VCFSX
  { 374,  3,  1,  67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 },  // Inst #374 = VCFUX
  { 375,  3,  1,  68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #375 = VCMPBFP
  { 376,  3,  1,  68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #376 = VCMPBFPo
  { 377,  3,  1,  68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #377 = VCMPEQFP
  { 378,  3,  1,  68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #378 = VCMPEQFPo
  { 379,  3,  1,  68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #379 = VCMPEQUB
  { 380,  3,  1,  68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #380 = VCMPEQUBo
  { 381,  3,  1,  68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #381 = VCMPEQUH
  { 382,  3,  1,  68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #382 = VCMPEQUHo
  { 383,  3,  1,  68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #383 = VCMPEQUW
  { 384,  3,  1,  68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #384 = VCMPEQUWo
  { 385,  3,  1,  68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #385 = VCMPGEFP
  { 386,  3,  1,  68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #386 = VCMPGEFPo
  { 387,  3,  1,  68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #387 = VCMPGTFP
  { 388,  3,  1,  68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #388 = VCMPGTFPo
  { 389,  3,  1,  68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #389 = VCMPGTSB
  { 390,  3,  1,  68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #390 = VCMPGTSBo
  { 391,  3,  1,  68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #391 = VCMPGTSH
  { 392,  3,  1,  68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #392 = VCMPGTSHo
  { 393,  3,  1,  68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #393 = VCMPGTSW
  { 394,  3,  1,  68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #394 = VCMPGTSWo
  { 395,  3,  1,  68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #395 = VCMPGTUB
  { 396,  3,  1,  68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #396 = VCMPGTUBo
  { 397,  3,  1,  68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #397 = VCMPGTUH
  { 398,  3,  1,  68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #398 = VCMPGTUHo
  { 399,  3,  1,  68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #399 = VCMPGTUW
  { 400,  3,  1,  68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList15, NULL, OperandInfo84 },  // Inst #400 = VCMPGTUWo
  { 401,  3,  1,  67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 },  // Inst #401 = VCTSXS
  { 402,  3,  1,  67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 },  // Inst #402 = VCTUXS
  { 403,  2,  1,  67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #403 = VEXPTEFP
  { 404,  2,  1,  67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #404 = VLOGEFP
  { 405,  4,  1,  67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #405 = VMADDFP
  { 406,  3,  1,  67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #406 = VMAXFP
  { 407,  3,  1,  67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #407 = VMAXSB
  { 408,  3,  1,  67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #408 = VMAXSH
  { 409,  3,  1,  67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #409 = VMAXSW
  { 410,  3,  1,  67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #410 = VMAXUB
  { 411,  3,  1,  67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #411 = VMAXUH
  { 412,  3,  1,  67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #412 = VMAXUW
  { 413,  4,  1,  67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #413 = VMHADDSHS
  { 414,  4,  1,  67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #414 = VMHRADDSHS
  { 415,  3,  1,  67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #415 = VMINFP
  { 416,  3,  1,  67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #416 = VMINSB
  { 417,  3,  1,  67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #417 = VMINSH
  { 418,  3,  1,  67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #418 = VMINSW
  { 419,  3,  1,  67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #419 = VMINUB
  { 420,  3,  1,  67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #420 = VMINUH
  { 421,  3,  1,  67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #421 = VMINUW
  { 422,  4,  1,  67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #422 = VMLADDUHM
  { 423,  3,  1,  67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #423 = VMRGHB
  { 424,  3,  1,  67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #424 = VMRGHH
  { 425,  3,  1,  67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #425 = VMRGHW
  { 426,  3,  1,  67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #426 = VMRGLB
  { 427,  3,  1,  67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #427 = VMRGLH
  { 428,  3,  1,  67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #428 = VMRGLW
  { 429,  4,  1,  67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #429 = VMSUMMBM
  { 430,  4,  1,  67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #430 = VMSUMSHM
  { 431,  4,  1,  67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #431 = VMSUMSHS
  { 432,  4,  1,  67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #432 = VMSUMUBM
  { 433,  4,  1,  67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #433 = VMSUMUHM
  { 434,  4,  1,  67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #434 = VMSUMUHS
  { 435,  3,  1,  67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #435 = VMULESB
  { 436,  3,  1,  67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #436 = VMULESH
  { 437,  3,  1,  67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #437 = VMULEUB
  { 438,  3,  1,  67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #438 = VMULEUH
  { 439,  3,  1,  67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #439 = VMULOSB
  { 440,  3,  1,  67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #440 = VMULOSH
  { 441,  3,  1,  67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #441 = VMULOUB
  { 442,  3,  1,  67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #442 = VMULOUH
  { 443,  4,  1,  67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #443 = VNMSUBFP
  { 444,  3,  1,  67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #444 = VNOR
  { 445,  3,  1,  67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #445 = VOR
  { 446,  4,  1,  67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #446 = VPERM
  { 447,  3,  1,  67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #447 = VPKPX
  { 448,  3,  1,  67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #448 = VPKSHSS
  { 449,  3,  1,  67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #449 = VPKSHUS
  { 450,  3,  1,  67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #450 = VPKSWSS
  { 451,  3,  1,  67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #451 = VPKSWUS
  { 452,  3,  1,  67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #452 = VPKUHUM
  { 453,  3,  1,  67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #453 = VPKUHUS
  { 454,  3,  1,  67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #454 = VPKUWUM
  { 455,  3,  1,  67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #455 = VPKUWUS
  { 456,  2,  1,  67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #456 = VREFP
  { 457,  2,  1,  67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #457 = VRFIM
  { 458,  2,  1,  67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #458 = VRFIN
  { 459,  2,  1,  67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #459 = VRFIP
  { 460,  2,  1,  67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #460 = VRFIZ
  { 461,  3,  1,  67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #461 = VRLB
  { 462,  3,  1,  67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #462 = VRLH
  { 463,  3,  1,  67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #463 = VRLW
  { 464,  2,  1,  67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #464 = VRSQRTEFP
  { 465,  4,  1,  67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 },  // Inst #465 = VSEL
  { 466,  3,  1,  67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #466 = VSL
  { 467,  3,  1,  67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #467 = VSLB
  { 468,  4,  1,  67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 },  // Inst #468 = VSLDOI
  { 469,  3,  1,  67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #469 = VSLH
  { 470,  3,  1,  67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #470 = VSLO
  { 471,  3,  1,  67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #471 = VSLW
  { 472,  3,  1,  71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 },  // Inst #472 = VSPLTB
  { 473,  3,  1,  71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 },  // Inst #473 = VSPLTH
  { 474,  2,  1,  71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 },  // Inst #474 = VSPLTISB
  { 475,  2,  1,  71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 },  // Inst #475 = VSPLTISH
  { 476,  2,  1,  71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 },  // Inst #476 = VSPLTISW
  { 477,  3,  1,  71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 },  // Inst #477 = VSPLTW
  { 478,  3,  1,  67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #478 = VSR
  { 479,  3,  1,  67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #479 = VSRAB
  { 480,  3,  1,  67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #480 = VSRAH
  { 481,  3,  1,  67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #481 = VSRAW
  { 482,  3,  1,  67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #482 = VSRB
  { 483,  3,  1,  67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #483 = VSRH
  { 484,  3,  1,  67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #484 = VSRO
  { 485,  3,  1,  67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #485 = VSRW
  { 486,  3,  1,  67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #486 = VSUBCUW
  { 487,  3,  1,  70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #487 = VSUBFP
  { 488,  3,  1,  67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #488 = VSUBSBS
  { 489,  3,  1,  67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #489 = VSUBSHS
  { 490,  3,  1,  67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #490 = VSUBSWS
  { 491,  3,  1,  70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #491 = VSUBUBM
  { 492,  3,  1,  67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #492 = VSUBUBS
  { 493,  3,  1,  70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #493 = VSUBUHM
  { 494,  3,  1,  67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #494 = VSUBUHS
  { 495,  3,  1,  70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #495 = VSUBUWM
  { 496,  3,  1,  67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #496 = VSUBUWS
  { 497,  3,  1,  67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #497 = VSUM2SWS
  { 498,  3,  1,  67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #498 = VSUM4SBS
  { 499,  3,  1,  67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #499 = VSUM4SHS
  { 500,  3,  1,  67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #500 = VSUM4UBS
  { 501,  3,  1,  67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #501 = VSUMSWS
  { 502,  2,  1,  67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #502 = VUPKHPX
  { 503,  2,  1,  67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #503 = VUPKHSB
  { 504,  2,  1,  67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #504 = VUPKHSH
  { 505,  2,  1,  67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #505 = VUPKLPX
  { 506,  2,  1,  67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #506 = VUPKLSB
  { 507,  2,  1,  67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 },  // Inst #507 = VUPKLSH
  { 508,  3,  1,  67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo84 },  // Inst #508 = VXOR
  { 509,  1,  1,  67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo61 },  // Inst #509 = V_SET0
  { 510,  3,  1,  14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 },  // Inst #510 = XOR
  { 511,  3,  1,  14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 },  // Inst #511 = XOR8
  { 512,  3,  1,  14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #512 = XORI
  { 513,  3,  1,  14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 },  // Inst #513 = XORI8
  { 514,  3,  1,  14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 },  // Inst #514 = XORIS
  { 515,  3,  1,  14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 },  // Inst #515 = XORIS8
};
} // End llvm namespace