LLVM API Documentation
#include "llvm/CodeGen/ScheduleDAGSDNodes.h"#include "llvm/CodeGen/SchedulerRegistry.h"#include "llvm/CodeGen/SelectionDAGISel.h"#include "llvm/Target/TargetRegisterInfo.h"#include "llvm/Target/TargetData.h"#include "llvm/Target/TargetMachine.h"#include "llvm/Target/TargetInstrInfo.h"#include "llvm/Support/Debug.h"#include "llvm/Support/Compiler.h"#include "llvm/ADT/PriorityQueue.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/Statistic.h"#include "llvm/ADT/STLExtras.h"#include <climits>#include "llvm/Support/CommandLine.h"
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Defines | |
| #define | DEBUG_TYPE "pre-RA-sched" |
Typedefs | |
| typedef RegReductionPriorityQueue < bu_ls_rr_sort > | BURegReductionPriorityQueue |
| typedef RegReductionPriorityQueue < td_ls_rr_sort > | TDRegReductionPriorityQueue |
Functions | |
| STATISTIC (NumBacktracks,"Number of times scheduler backtracked") | |
| STATISTIC (NumUnfolds,"Number of nodes unfolded") | |
| STATISTIC (NumDups,"Number of duplicated nodes") | |
| STATISTIC (NumPRCopies,"Number of physical register copies") | |
| static MVT | getPhysicalRegisterVT (SDNode *N, unsigned Reg, const TargetInstrInfo *TII) |
| static bool | isCopyFromLiveIn (const SUnit *SU) |
| static unsigned | CalcNodeSethiUllmanNumber (const SUnit *SU, std::vector< unsigned > &SUNumbers) |
| static unsigned | closestSucc (const SUnit *SU) |
| static unsigned | calcMaxScratches (const SUnit *SU) |
| static bool | hasCopyToRegUse (const SUnit *SU) |
| static bool | canClobberPhysRegDefs (const SUnit *SuccSU, const SUnit *SU, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) |
| static unsigned | LimitedSumOfUnscheduledPredsOfSuccs (const SUnit *SU, unsigned Limit) |
| ScheduleDAG * | llvm::createBURRListDAGScheduler (SelectionDAGISel *IS, bool Fast) |
| ScheduleDAG * | llvm::createTDRRListDAGScheduler (SelectionDAGISel *IS, bool Fast) |
Variables | |
| static RegisterScheduler | burrListDAGScheduler ("list-burr","Bottom-up register reduction list scheduling", createBURRListDAGScheduler) |
| static RegisterScheduler | tdrListrDAGScheduler ("list-tdrr","Top-down register reduction list scheduling", createTDRRListDAGScheduler) |
| #define DEBUG_TYPE "pre-RA-sched" |
Definition at line 18 of file ScheduleDAGRRList.cpp.
typedef RegReductionPriorityQueue<bu_ls_rr_sort> BURegReductionPriorityQueue [static] |
Definition at line 1038 of file ScheduleDAGRRList.cpp.
typedef RegReductionPriorityQueue<td_ls_rr_sort> TDRegReductionPriorityQueue [static] |
Definition at line 1041 of file ScheduleDAGRRList.cpp.
calcMaxScratches - Returns an cost estimate of the worse case requirement for scratch registers. Live-in operands and live-out results don't count since they are "fixed".
Definition at line 1065 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyFromReg, llvm::ISD::CopyToReg, E, llvm::SUnit::Preds, and llvm::SUnit::Succs.
| static unsigned CalcNodeSethiUllmanNumber | ( | const SUnit * | SU, | |
| std::vector< unsigned > & | SUNumbers | |||
| ) | [static] |
CalcNodeSethiUllmanNumber - Compute Sethi Ullman number. Smaller number is the higher priority.
Definition at line 892 of file ScheduleDAGRRList.cpp.
References E, llvm::SUnit::NodeNum, and llvm::SUnit::Preds.
| static bool canClobberPhysRegDefs | ( | const SUnit * | SuccSU, | |
| const SUnit * | SU, | |||
| const TargetInstrInfo * | TII, | |||
| const TargetRegisterInfo * | TRI | |||
| ) | [static] |
canClobberPhysRegDefs - True if SU would clobber one of SuccSU's physical register defs.
Definition at line 1169 of file ScheduleDAGRRList.cpp.
References llvm::TargetInstrInfo::get(), llvm::SDNode::getMachineOpcode(), llvm::SUnit::getNode(), llvm::SDNode::getNumValues(), llvm::SDNode::getValueType(), llvm::SDNode::hasAnyUseOfValue(), ImpDefs, and llvm::TargetRegisterInfo::regsOverlap().
closestSucc - Returns the scheduled cycle of the successor which is closet to the current cycle.
Definition at line 1046 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyToReg, E, and llvm::SUnit::Succs.
| static MVT getPhysicalRegisterVT | ( | SDNode * | N, | |
| unsigned | Reg, | |||
| const TargetInstrInfo * | TII | |||
| ) | [static] |
getPhysicalRegisterVT - Returns the ValueType of the physical register definition of the specified node. FIXME: Move to SelectionDAG?
Definition at line 563 of file ScheduleDAGRRList.cpp.
References llvm::TargetInstrInfo::get(), llvm::TargetInstrDesc::getImplicitDefs(), llvm::SDNode::getMachineOpcode(), llvm::TargetInstrDesc::getNumDefs(), llvm::SDNode::getValueType(), and llvm::TargetInstrDesc::ImplicitDefs.
| static bool hasCopyToRegUse | ( | const SUnit * | SU | ) | [static] |
hasCopyToRegUse - Return true if SU has a value successor that is a CopyToReg node.
Definition at line 1156 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyToReg, E, llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), and llvm::SUnit::Succs.
| static bool isCopyFromLiveIn | ( | const SUnit * | SU | ) | [inline, static] |
Definition at line 883 of file ScheduleDAGRRList.cpp.
References llvm::ISD::CopyFromReg, llvm::SUnit::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), and llvm::SDNode::getOperand().
LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled predecessors of the successors of the SUnit SU. Stop when the provided limit is exceeded.
Definition at line 1280 of file ScheduleDAGRRList.cpp.
References E, II, llvm::SUnit::isScheduled, llvm::SUnit::Preds, and llvm::SUnit::Succs.
| STATISTIC | ( | NumPRCopies | , | |
| "Number of physical register copies" | ||||
| ) |
| STATISTIC | ( | NumDups | , | |
| "Number of duplicated nodes" | ||||
| ) |
| STATISTIC | ( | NumUnfolds | , | |
| "Number of nodes unfolded" | ||||
| ) |
| STATISTIC | ( | NumBacktracks | , | |
| "Number of times scheduler backtracked" | ||||
| ) |
AvailableQueue - The priority queue to use for the available SUnits.
Definition at line 62 of file ScheduleDAGRRList.cpp.
RegisterScheduler burrListDAGScheduler("list-burr","Bottom-up register reduction list scheduling", createBURRListDAGScheduler) [static] |
Definition at line 923 of file ScheduleDAGRRList.cpp.
| bool isBottomUp |
isBottomUp - This is true if the scheduling problem is bottom-up, false if it is top-down.
Definition at line 59 of file ScheduleDAGRRList.cpp.
Referenced by llvm::ScheduleDAG::VerifySchedule().
| std::vector<unsigned> LiveRegCycles |
Definition at line 69 of file ScheduleDAGRRList.cpp.
| std::vector<SUnit*> LiveRegDefs |
Definition at line 68 of file ScheduleDAGRRList.cpp.
LiveRegDefs - A set of physical registers and their definition that are "live". These nodes must be scheduled before any other nodes that modifies the registers can be scheduled.
Definition at line 67 of file ScheduleDAGRRList.cpp.
| PriorityQueue<SUnit*, std::vector<SUnit*>, SF> Queue |
Definition at line 922 of file ScheduleDAGRRList.cpp.
| ScheduleDAGRRList* scheduleDAG |
Definition at line 931 of file ScheduleDAGRRList.cpp.
| std::vector<unsigned> SethiUllmanNumbers |
Definition at line 934 of file ScheduleDAGRRList.cpp.
| RegReductionPriorityQueue<td_ls_rr_sort>* SPQ |
Definition at line 867 of file ScheduleDAGRRList.cpp.
Definition at line 927 of file ScheduleDAGRRList.cpp.
Referenced by llvm::ScheduleDAG::VerifySchedule().
RegisterScheduler tdrListrDAGScheduler("list-tdrr","Top-down register reduction list scheduling", createTDRRListDAGScheduler) [static] |
| const TargetInstrInfo* TII |
Definition at line 929 of file ScheduleDAGRRList.cpp.
Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.
Definition at line 73 of file ScheduleDAGRRList.cpp.
| const TargetRegisterInfo* TRI |
Definition at line 930 of file ScheduleDAGRRList.cpp.