SelectionDAGBuild.cpp File Reference

#include "SelectionDAGBuild.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Constants.h"
#include "llvm/CallingConv.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/GlobalVariable.h"
#include "llvm/InlineAsm.h"
#include "llvm/Instructions.h"
#include "llvm/Intrinsics.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/Module.h"
#include "llvm/CodeGen/FastISel.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/GCMetadata.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/DwarfWriter.h"
#include "llvm/Analysis/DebugInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include "llvm/Instruction.def"
#include "llvm/CodeGen/SelectionDAGISel.h"

Include dependency graph for SelectionDAGBuild.cpp:

Go to the source code of this file.

Namespaces
namespace	llvm
Classes
struct	llvm::RegsForValue
struct	llvm::SDISelAsmOperandInfo
Defines
#define	DEBUG_TYPE   "isel"
#define	HANDLE_INST(NUM, OPCODE, CLASS)   case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
Functions
static unsigned	ComputeLinearIndex (const TargetLowering &TLI, const Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex=0)
static void	ComputeValueVTs (const TargetLowering &TLI, const Type *Ty, SmallVectorImpl< MVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=0, uint64_t StartingOffset=0)
static bool	isUsedOutsideOfDefiningBlock (Instruction *I)
static bool	isOnlyUsedInEntryBlock (Argument *A, bool EnableFastISel)
static SDValue	getCopyFromParts (SelectionDAG &DAG, DebugLoc dl, const SDValue *Parts, unsigned NumParts, MVT PartVT, MVT ValueVT, ISD::NodeType AssertOp=ISD::DELETED_NODE)
static void	getCopyToParts (SelectionDAG &DAG, DebugLoc dl, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, ISD::NodeType ExtendKind=ISD::ANY_EXTEND)
static bool	InBlock (const Value *V, const BasicBlock *BB)
static ISD::CondCode	getFCmpCondCode (FCmpInst::Predicate Pred)
static ISD::CondCode	getICmpCondCode (ICmpInst::Predicate Pred)
static bool	areJTsAllowed (const TargetLowering &TLI)
static APInt	ComputeRange (const APInt &First, const APInt &Last)
static bool	SequentialMask (SDValue Mask, unsigned SIndx)
static GlobalVariable *	ExtractTypeInfo (Value *V)
	ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
void	llvm::AddCatchInfo (CallInst &I, MachineModuleInfo *MMI, MachineBasicBlock *MBB)
static SDValue	GetSignificand (SelectionDAG &DAG, SDValue Op, DebugLoc dl)
static SDValue	GetExponent (SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, DebugLoc dl)
static SDValue	getF32Constant (SelectionDAG &DAG, unsigned Flt)
	getF32Constant - Get 32-bit floating point constant.
static const TargetRegisterClass *	isAllocatableRegister (unsigned Reg, MachineFunction &MF, const TargetLowering &TLI, const TargetRegisterInfo *TRI)
static bool	hasInlineAsmMemConstraint (std::vector< InlineAsm::ConstraintInfo > &CInfos, const TargetLowering &TLI)
Variables
static unsigned	LimitFloatPrecision
static cl::opt< unsigned, true >	LimitFPPrecision ("limit-float-precision", cl::desc("Generate low-precision inline sequences ""for some float libcalls"), cl::location(LimitFloatPrecision), cl::init(0))

---

Define Documentation

#define DEBUG_TYPE   "isel"

Definition at line 14 of file SelectionDAGBuild.cpp.

#define HANDLE_INST	(	NUM,
		OPCODE,
		CLASS		)	case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);

---

Function Documentation

static bool areJTsAllowed

(

const TargetLowering &

TLI

)

[inline, static]

Definition at line 1661 of file SelectionDAGBuild.cpp.

References llvm::ISD::BR_JT, llvm::ISD::BRIND, llvm::DisableJumpTables, llvm::TargetLowering::isOperationLegalOrCustom(), and llvm::MVT::Other.

static unsigned ComputeLinearIndex	(	const TargetLowering &	TLI,
		const Type *	Ty,
		const unsigned *	Indices,
		const unsigned *	IndicesEnd,
		unsigned	CurIndex = 0
	)			[static]

ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence of insertvalue or extractvalue indices that identify a member, return the linearized index of the start of the member.

Definition at line 72 of file SelectionDAGBuild.cpp.

static APInt ComputeRange	(	const APInt &	First,
		const APInt &	Last
	)			[static]

Definition at line 1667 of file SelectionDAGBuild.cpp.

References llvm::APInt::getBitWidth(), and llvm::APInt::sext().

static void ComputeValueVTs	(	const TargetLowering &	TLI,
		const Type *	Ty,
		SmallVectorImpl< MVT > &	ValueVTs,
		SmallVectorImpl< uint64_t > *	Offsets = 0,
		uint64_t	StartingOffset = 0
	)			[static]

ComputeValueVTs - Given an LLVM IR type, compute a sequence of MVTs that represent all the individual underlying non-aggregate types that comprise it.

If Offsets is non-null, it points to a vector to be filled in with the in-memory offsets of each of the individual values.

Definition at line 113 of file SelectionDAGBuild.cpp.

References llvm::StructLayout::getElementOffset(), llvm::TargetData::getStructLayout(), llvm::TargetLowering::getTargetData(), llvm::TargetData::getTypePaddedSize(), llvm::TargetLowering::getValueType(), and llvm::SmallVectorImpl< T >::push_back().

Referenced by llvm::FunctionLoweringInfo::CreateRegForValue(), llvm::SelectionDAGLowering::getValue(), llvm::TargetLowering::LowerArguments(), llvm::TargetLowering::LowerCallTo(), llvm::RegsForValue::RegsForValue(), and llvm::FunctionLoweringInfo::set().

static GlobalVariable* ExtractTypeInfo

(

Value *

V

)

[static]

ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.

Definition at line 2980 of file SelectionDAGBuild.cpp.

References llvm::dyn_cast(), GV, and llvm::Value::stripPointerCasts().

Referenced by llvm::AddCatchInfo().

static SDValue getCopyFromParts	(	SelectionDAG &	DAG,
		DebugLoc	dl,
		const SDValue *	Parts,
		unsigned	NumParts,
		MVT	PartVT,
		MVT	ValueVT,
		ISD::NodeType	AssertOp = ISD::DELETED_NODE
	)			[static]

getCopyFromParts - Create a value that contains the specified legal parts combined into the value they represent. If the parts combine to a type larger then ValueVT then AssertOp can be used to specify whether the extra bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT (ISD::AssertSext).

Definition at line 423 of file SelectionDAGBuild.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::BIT_CONVERT, llvm::MVT::bitsLT(), llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::DELETED_NODE, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::MVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::getPointerTy(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getValueType(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::TargetLowering::getVectorTypeBreakdown(), llvm::SPISD::Hi, llvm::TargetLowering::isBigEndian(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::MVT::isVector(), llvm::SPISD::Lo, llvm::Log2_32(), llvm::ISD::OR, llvm::ISD::SHL, std::swap(), llvm::FunctionLoweringInfo::TLI, llvm::ISD::TRUNCATE, Val, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RegsForValue::getCopyFromRegs(), llvm::TargetLowering::LowerArguments(), and llvm::TargetLowering::LowerCallTo().

static void getCopyToParts	(	SelectionDAG &	DAG,
		DebugLoc	dl,
		SDValue	Val,
		SDValue *	Parts,
		unsigned	NumParts,
		MVT	PartVT,
		ISD::NodeType	ExtendKind = ISD::ANY_EXTEND
	)			[static]

getCopyToParts - Create a series of nodes that contain the specified value split into legal parts. If the parts contain more bits than Val, then, for integers, ExtendKind can be used to specify how to generate the extra bits.

Definition at line 571 of file SelectionDAGBuild.cpp.

References llvm::ISD::BIT_CONVERT, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::getPointerTy(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::TargetLowering::getVectorTypeBreakdown(), llvm::TargetLowering::isBigEndian(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::TargetLowering::isTypeLegal(), llvm::MVT::isVector(), llvm::Log2_32(), llvm::ISD::SRL, llvm::FunctionLoweringInfo::TLI, and llvm::ISD::TRUNCATE.

Referenced by llvm::RegsForValue::getCopyToRegs(), and llvm::TargetLowering::LowerCallTo().

static SDValue GetExponent	(	SelectionDAG &	DAG,
		SDValue	Op,
		const TargetLowering &	TLI,
		DebugLoc	dl
	)			[static]

GetExponent - Get the exponent:

(float)(int)(((Op & 0x7f800000) >> 23) - 127);

where Op is the hexidecimal representation of floating point value.

Definition at line 3067 of file SelectionDAGBuild.cpp.

References llvm::ISD::AND, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::getPointerTy(), llvm::MVT::i32, llvm::ISD::SINT_TO_FP, llvm::ISD::SRL, and llvm::ISD::SUB.

static SDValue getF32Constant	(	SelectionDAG &	DAG,
		unsigned	Flt
	)			[static]

getF32Constant - Get 32-bit floating point constant.

Definition at line 3080 of file SelectionDAGBuild.cpp.

References llvm::lltok::APFloat, llvm::MVT::f32, and llvm::SelectionDAG::getConstantFP().

static ISD::CondCode getFCmpCondCode

(

FCmpInst::Predicate

Pred

)

[static]

getFCmpCondCode - Return the ISD condition code corresponding to the given LLVM IR floating-point condition code. This includes consideration of global floating-point math flags.

Definition at line 1065 of file SelectionDAGBuild.cpp.

References llvm::CmpInst::FCMP_FALSE, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_TRUE, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, llvm::FiniteOnlyFPMath(), llvm::ISD::SETEQ, llvm::ISD::SETFALSE, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETTRUE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

Referenced by llvm::SelectionDAGLowering::EmitBranchForMergedCondition().

static ISD::CondCode getICmpCondCode

(

ICmpInst::Predicate

Pred

)

[static]

getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition code.

Definition at line 1098 of file SelectionDAGBuild.cpp.

References llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.

Referenced by llvm::SelectionDAGLowering::EmitBranchForMergedCondition().

static SDValue GetSignificand	(	SelectionDAG &	DAG,
		SDValue	Op,
		DebugLoc	dl
	)			[static]

GetSignificand - Get the significand and build it into a floating-point number with exponent of 1:

Op = (Op & 0x007fffff) | 0x3f800000;

where Op is the hexidecimal representation of floating point value.

Definition at line 3053 of file SelectionDAGBuild.cpp.

References llvm::ISD::AND, llvm::ISD::BIT_CONVERT, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, and llvm::ISD::OR.

static bool hasInlineAsmMemConstraint	(	std::vector< InlineAsm::ConstraintInfo > &	CInfos,
		const TargetLowering &	TLI
	)			[static]

hasInlineAsmMemConstraint - Return true if the inline asm instruction being processed uses a memory 'm' constraint.

Definition at line 4971 of file SelectionDAGBuild.cpp.

References llvm::TargetLowering::C_Memory, llvm::InlineAsm::ConstraintInfo::Codes, and llvm::TargetLowering::getConstraintType().

static bool InBlock	(	const Value *	V,
		const BasicBlock *	BB
	)			[static]

Definition at line 1055 of file SelectionDAGBuild.cpp.

References llvm::Instruction::getParent().

Referenced by llvm::SelectionDAGLowering::FindMergedConditions().

static const TargetRegisterClass* isAllocatableRegister	(	unsigned	Reg,
		MachineFunction &	MF,
		const TargetLowering &	TLI,
		const TargetRegisterInfo *	TRI
	)			[static]

isAllocatableRegister - If the specified register is safe to allocate, i.e. it isn't a stack pointer or some other special register, return the register class for the register. Otherwise, return null.

Definition at line 4647 of file SelectionDAGBuild.cpp.

References llvm::TargetRegisterClass::allocation_order_begin(), llvm::TargetRegisterClass::allocation_order_end(), llvm::MVT::bitsLT(), E, llvm::TargetLowering::isTypeLegal(), llvm::MVT::Other, llvm::TargetRegisterInfo::regclass_begin(), llvm::TargetRegisterInfo::regclass_end(), llvm::TargetRegisterClass::vt_begin(), and llvm::TargetRegisterClass::vt_end().

Referenced by llvm::SelectionDAGLowering::GetRegistersForValue().

static bool isOnlyUsedInEntryBlock	(	Argument *	A,
		bool	EnableFastISel
	)			[static]

isOnlyUsedInEntryBlock - If the specified argument is only used in the entry block, return true. This includes arguments used by switches, since the switch may expand into multiple basic blocks.

Definition at line 254 of file SelectionDAGBuild.cpp.

References llvm::Function::begin(), E, Entry, llvm::Argument::getParent(), llvm::Argument::hasByValAttr(), llvm::Value::use_begin(), llvm::Value::use_empty(), and llvm::Value::use_end().

Referenced by llvm::FunctionLoweringInfo::set().

static bool isUsedOutsideOfDefiningBlock

(

Instruction *

I

)

[static]

isUsedOutsideOfDefiningBlock - Return true if this instruction is used by PHI nodes or outside of the basic block that defines it, or used by a switch or atomic instruction, which may expand to multiple basic blocks.

Definition at line 240 of file SelectionDAGBuild.cpp.

References BB, E, llvm::Instruction::getParent(), llvm::Value::use_begin(), and llvm::Value::use_end().

Referenced by llvm::FunctionLoweringInfo::set().

static bool SequentialMask	(	SDValue	Mask,
		unsigned	SIndx
	)			[static]

Definition at line 2387 of file SelectionDAGBuild.cpp.

References llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), Idx, and llvm::ISD::UNDEF.

---

Variable Documentation

unsigned LimitFloatPrecision [static]

LimitFloatPrecision - Generate low-precision inline sequences for some float libcalls (6, 8 or 12 bits).

Definition at line 59 of file SelectionDAGBuild.cpp.

cl::opt<unsigned, true> LimitFPPrecision("limit-float-precision", cl::desc("Generate low-precision inline sequences ""for some float libcalls"), cl::location(LimitFloatPrecision), cl::init(0)) [static]