SelectionDAGISel.cpp File Reference

#include "llvm/CodeGen/SelectionDAGISel.h"
#include "SelectionDAGBuild.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Constants.h"
#include "llvm/CallingConv.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/GlobalVariable.h"
#include "llvm/InlineAsm.h"
#include "llvm/Instructions.h"
#include "llvm/Intrinsics.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/CodeGen/FastISel.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/GCMetadata.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ScheduleDAGSDNodes.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/DwarfWriter.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Timer.h"
#include <algorithm>

Include dependency graph for SelectionDAGISel.cpp:

Go to the source code of this file.

Namespaces
namespace	llvm
Defines
#define	DEBUG_TYPE   "isel"
Functions
ScheduleDAG *	llvm::createDefaultScheduler (SelectionDAGISel *IS, bool Fast)
static void	EmitLiveInCopy (MachineBasicBlock *MBB, MachineBasicBlock::iterator &InsertPos, unsigned VirtReg, unsigned PhysReg, const TargetRegisterClass *RC, DenseMap< MachineInstr *, unsigned > &CopyRegMap, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
static void	EmitLiveInCopies (MachineBasicBlock *EntryMBB, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
static void	copyCatchInfo (BasicBlock *SrcBB, BasicBlock *DestBB, MachineModuleInfo *MMI, FunctionLoweringInfo &FLI)
static bool	IsFixedFrameObjectWithPosOffset (MachineFrameInfo *MFI, SDValue Op)
static bool	IsPossiblyOverwrittenArgumentOfTailCall (SDValue Op, MachineFrameInfo *MFI)
static void	CheckDAGForTailCallsAndFixThem (SelectionDAG &DAG, const TargetLowering &TLI)
Variables
static cl::opt< bool >	EnableValueProp ("enable-value-prop", cl::Hidden)
static cl::opt< bool >	DisableLegalizeTypes ("disable-legalize-types", cl::Hidden)
static cl::opt< bool >	EnableFastISelVerbose ("fast-isel-verbose", cl::Hidden, cl::desc("Enable verbose messages in the \"fast\" ""instruction selector"))
static cl::opt< bool >	EnableFastISelAbort ("fast-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"fast\" instruction fails"))
static cl::opt< bool >	SchedLiveInCopies ("schedule-livein-copies", cl::desc("Schedule copies of livein registers"), cl::init(false))
static cl::opt< bool >	ViewDAGCombine1 ("view-dag-combine1-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the first ""dag combine pass"))
static cl::opt< bool >	ViewLegalizeTypesDAGs ("view-legalize-types-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize types"))
static cl::opt< bool >	ViewLegalizeDAGs ("view-legalize-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize"))
static cl::opt< bool >	ViewDAGCombine2 ("view-dag-combine2-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the second ""dag combine pass"))
static cl::opt< bool >	ViewDAGCombineLT ("view-dag-combine-lt-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the post legalize types"" dag combine pass"))
static cl::opt< bool >	ViewISelDAGs ("view-isel-dags", cl::Hidden, cl::desc("Pop up a window to show isel dags as they are selected"))
static cl::opt< bool >	ViewSchedDAGs ("view-sched-dags", cl::Hidden, cl::desc("Pop up a window to show sched dags as they are processed"))
static cl::opt< bool >	ViewSUnitDAGs ("view-sunit-dags", cl::Hidden, cl::desc("Pop up a window to show SUnit dags after they are processed"))
static cl::opt < RegisterScheduler::FunctionPassCtor, false, RegisterPassParser < RegisterScheduler > >	ISHeuristic ("pre-RA-sched", cl::init(&createDefaultScheduler), cl::desc("Instruction schedulers available (before register"" allocation):"))
static RegisterScheduler	defaultListDAGScheduler ("default","Best scheduler for the target", createDefaultScheduler)

---

Define Documentation

#define DEBUG_TYPE   "isel"

Definition at line 14 of file SelectionDAGISel.cpp.

---

Function Documentation

static void CheckDAGForTailCallsAndFixThem	(	SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)			[static]

CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the DAG and fixes their tailcall attribute operand.

Definition at line 398 of file SelectionDAGISel.cpp.

References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), Arg, llvm::SmallVectorImpl< T >::begin(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::TargetLowering::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getRoot(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::TargetLowering::IsEligibleForTailCallOptimization(), IsPossiblyOverwrittenArgumentOfTailCall(), llvm::SelectionDAGISel::MF, MFI, llvm::SmallVectorImpl< T >::push_back(), llvm::ISD::RET, llvm::MipsISD::Ret, llvm::SmallVectorImpl< T >::size(), llvm::TID::Terminator, llvm::SelectionDAG::UpdateNodeOperands(), and VT.

static void copyCatchInfo	(	BasicBlock *	SrcBB,
		BasicBlock *	DestBB,
		MachineModuleInfo *	MMI,
		FunctionLoweringInfo &	FLI
	)			[static]

Definition at line 349 of file SelectionDAGISel.cpp.

References llvm::AddCatchInfo(), llvm::BasicBlock::begin(), llvm::FunctionLoweringInfo::CatchInfoFound, E, llvm::BasicBlock::end(), and llvm::FunctionLoweringInfo::MBBMap.

static void EmitLiveInCopies	(	MachineBasicBlock *	EntryMBB,
		const MachineRegisterInfo &	MRI,
		const TargetRegisterInfo &	TRI,
		const TargetInstrInfo &	TII
	)			[static]

EmitLiveInCopies - If this is the first basic block in the function, and if it has live ins that need to be copied into vregs, emit the copies into the block.

Definition at line 236 of file SelectionDAGISel.cpp.

References llvm::MachineBasicBlock::begin(), llvm::TargetInstrInfo::copyRegToReg(), E, EmitLiveInCopy(), llvm::MachineRegisterInfo::getRegClass(), InsertPos, LI, llvm::MachineRegisterInfo::livein_begin(), llvm::MachineRegisterInfo::livein_end(), and SchedLiveInCopies.

Referenced by llvm::SelectionDAGISel::runOnFunction().

static void EmitLiveInCopy	(	MachineBasicBlock *	MBB,
		MachineBasicBlock::iterator &	InsertPos,
		unsigned	VirtReg,
		unsigned	PhysReg,
		const TargetRegisterClass *	RC,
		DenseMap< MachineInstr *, unsigned > &	CopyRegMap,
		const MachineRegisterInfo &	MRI,
		const TargetRegisterInfo &	TRI,
		const TargetInstrInfo &	TII
	)			[static]

EmitLiveInCopy - Emit a copy for a live in physical register. If the physical register has only a single copy use, then coalesced the copy if possible.

Definition at line 171 of file SelectionDAGISel.cpp.

References llvm::MachineBasicBlock::begin(), llvm::TargetInstrInfo::copyRegToReg(), llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::end(), llvm::MachineBasicBlock::erase(), llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::find(), if(), llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::insert(), llvm::TargetInstrInfo::isMoveInstr(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::prior(), llvm::TargetRegisterInfo::regsOverlap(), llvm::MachineRegisterInfo::use_begin(), and llvm::MachineRegisterInfo::use_end().

Referenced by EmitLiveInCopies().

static bool IsFixedFrameObjectWithPosOffset	(	MachineFrameInfo *	MFI,
		SDValue	Op
	)			[static]

IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and whether object offset >= 0.

Definition at line 365 of file SelectionDAGISel.cpp.

References llvm::dyn_cast(), FrameIdx, llvm::FrameIndexSDNode::getIndex(), llvm::MachineFrameInfo::getObjectOffset(), and llvm::MachineFrameInfo::isFixedObjectIndex().

Referenced by IsPossiblyOverwrittenArgumentOfTailCall().

static bool IsPossiblyOverwrittenArgumentOfTailCall	(	SDValue	Op,
		MachineFrameInfo *	MFI
	)			[static]

IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could possibly be overwritten when lowering the outgoing arguments in a tail call. Currently the implementation of this call is very conservative and assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with virtual registers would be overwritten by direct lowering.

Definition at line 379 of file SelectionDAGISel.cpp.

References llvm::ISD::CopyFromReg, llvm::dyn_cast(), llvm::TargetRegisterInfo::FirstVirtualRegister, llvm::ISD::FORMAL_ARGUMENTS, getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), IsFixedFrameObjectWithPosOffset(), llvm::ISD::LOAD, and llvm::ISD::MERGE_VALUES.

Referenced by CheckDAGForTailCallsAndFixThem().

---

Variable Documentation

RegisterScheduler defaultListDAGScheduler("default","Best scheduler for the target", createDefaultScheduler) [static]

cl::opt<bool> DisableLegalizeTypes("disable-legalize-types", cl::Hidden) [static]

cl::opt<bool> EnableFastISelAbort("fast-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"fast\" instruction fails")) [static]

Referenced by llvm::SelectionDAGISel::runOnFunction().

cl::opt<bool> EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, cl::desc("Enable verbose messages in the \"fast\" ""instruction selector")) [static]

cl::opt<bool> EnableValueProp("enable-value-prop", cl::Hidden) [static]

cl::opt<RegisterScheduler::FunctionPassCtor, false, RegisterPassParser<RegisterScheduler> > ISHeuristic("pre-RA-sched", cl::init(&createDefaultScheduler), cl::desc("Instruction schedulers available (before register"" allocation):")) [static]

ISHeuristic command line option for instruction schedulers.

cl::opt<bool> SchedLiveInCopies("schedule-livein-copies", cl::desc("Schedule copies of livein registers"), cl::init(false)) [static]

Referenced by EmitLiveInCopies().

cl::opt<bool> ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the first ""dag combine pass")) [static]

cl::opt<bool> ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the second ""dag combine pass")) [static]

cl::opt<bool> ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the post legalize types"" dag combine pass")) [static]

cl::opt<bool> ViewISelDAGs("view-isel-dags", cl::Hidden, cl::desc("Pop up a window to show isel dags as they are selected")) [static]

cl::opt<bool> ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize")) [static]

cl::opt<bool> ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize types")) [static]

cl::opt<bool> ViewSchedDAGs("view-sched-dags", cl::Hidden, cl::desc("Pop up a window to show sched dags as they are processed")) [static]

cl::opt<bool> ViewSUnitDAGs("view-sunit-dags", cl::Hidden, cl::desc("Pop up a window to show SUnit dags after they are processed")) [static]