1.5.6Copyright © 2003-2007 University of Illinois at Urbana-Champaign. All Rights Reserved.
LLVM API Documentation
#include "X86.h"#include "X86InstrBuilder.h"#include "X86ISelLowering.h"#include "X86MachineFunctionInfo.h"#include "X86TargetMachine.h"#include "llvm/CallingConv.h"#include "llvm/Constants.h"#include "llvm/DerivedTypes.h"#include "llvm/GlobalVariable.h"#include "llvm/Function.h"#include "llvm/Intrinsics.h"#include "llvm/ADT/BitVector.h"#include "llvm/ADT/VectorExtras.h"#include "llvm/CodeGen/CallingConvLower.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineModuleInfo.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/PseudoSourceValue.h"#include "llvm/CodeGen/SelectionDAG.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/Debug.h"#include "llvm/Target/TargetOptions.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/StringExtras.h"#include "llvm/Support/CommandLine.h"#include "X86GenCallingConv.inc"
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| static unsigned AddLiveIn | ( | MachineFunction & | MF, | |
| unsigned | PReg, | |||
| const TargetRegisterClass * | RC | |||
| ) | [static] |
AddLiveIn - This helper function adds the specified physical register to the MachineFunction as a live in value. It also creates a corresponding virtual register for it.
Definition at line 1096 of file X86ISelLowering.cpp.
References llvm::MachineRegisterInfo::addLiveIn(), llvm::TargetRegisterClass::contains(), llvm::MachineRegisterInfo::createVirtualRegister(), and llvm::MachineFunction::getRegInfo().
| static bool ArgsAreStructReturn | ( | SDValue | Op | ) | [static] |
ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct return semantics.
Definition at line 1116 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), and llvm::SDValue::getOperand().
| static bool CallIsStructReturn | ( | CallSDNode * | TheCall | ) | [static] |
CallIsStructReturn - Determines whether a CALL node uses struct return semantics.
Definition at line 1106 of file X86ISelLowering.cpp.
References llvm::CallSDNode::getArgFlags(), llvm::CallSDNode::getNumArgs(), and llvm::ISD::ArgFlagsTy::isSRet().
| static SDValue CanonicalizeMovddup | ( | SDValue | Op, | |
| SDValue | V1, | |||
| SDValue | Mask, | |||
| SelectionDAG & | DAG, | |||
| bool | HasSSE3 | |||
| ) | [static] |
CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
Definition at line 3067 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, isVectorLoad(), llvm::ISD::UNDEF, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::ISD::VECTOR_SHUFFLE.
| static SDValue CommuteVectorShuffle | ( | SDValue | Op, | |
| SDValue & | V1, | |||
| SDValue & | V2, | |||
| SDValue & | Mask, | |||
| SelectionDAG & | DAG | |||
| ) | [static] |
CommuteVectorShuffle - Swap vector_shuffle operands as well as values in ther permute mask.
Definition at line 2709 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), std::swap(), llvm::ISD::UNDEF, and llvm::ISD::VECTOR_SHUFFLE.
| static SDValue CommuteVectorShuffleMask | ( | SDValue | Mask, | |
| SelectionDAG & | DAG | |||
| ) | [static] |
CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming the two vector operands have swapped position.
Definition at line 2740 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), and llvm::ISD::UNDEF.
Referenced by LowerVECTOR_SHUFFLE_4wide(), and LowerVECTOR_SHUFFLEv8i16().
| static SDValue CreateCopyOfByValArgument | ( | SDValue | Src, | |
| SDValue | Dst, | |||
| SDValue | Chain, | |||
| ISD::ArgFlagsTy | Flags, | |||
| SelectionDAG & | DAG | |||
| ) | [static] |
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" with size and alignment information specified by the specific parameter attribute. The copy will be passed as a byval function parameter.
Definition at line 1198 of file X86ISelLowering.cpp.
References llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemcpy(), and llvm::MVT::i32.
| static bool EltsFromConsecutiveLoads | ( | SDNode * | N, | |
| SDValue | PermMask, | |||
| unsigned | NumElems, | |||
| MVT | EVT, | |||
| SDNode *& | Base, | |||
| SelectionDAG & | DAG, | |||
| MachineFrameInfo * | MFI, | |||
| const TargetLowering & | TLI | |||
| ) | [static] |
Definition at line 7557 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getShuffleScalarElt(), llvm::MVT::getSizeInBits(), llvm::TargetLowering::isConsecutiveLoad(), llvm::ISD::isNON_EXTLoad(), and llvm::ISD::UNDEF.
Referenced by PerformShuffleCombine().
| static SDValue EmitTailCallStoreRetAddr | ( | SelectionDAG & | DAG, | |
| MachineFunction & | MF, | |||
| SDValue | Chain, | |||
| SDValue | RetAddrFrIdx, | |||
| bool | Is64Bit, | |||
| int | FPDiff | |||
| ) | [static] |
EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call optimization is performed and it is required (FPDiff!=0).
Definition at line 1511 of file X86ISelLowering.cpp.
References llvm::MachineFrameInfo::CreateFixedObject(), llvm::PseudoSourceValue::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getStore(), llvm::MVT::i32, and llvm::MVT::i64.
getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.
Definition at line 833 of file X86ISelLowering.cpp.
Referenced by llvm::X86TargetLowering::getByValTypeAlignment().
| static SDValue getMOVLMask | ( | unsigned | NumElems, | |
| SelectionDAG & | DAG | |||
| ) | [static] |
getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd operation of specified width.
Definition at line 2964 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().
| static unsigned getNumOfConsecutiveZeros | ( | SDValue | Op, | |
| SDValue | Mask, | |||
| unsigned | NumElems, | |||
| bool | Low, | |||
| SelectionDAG & | DAG | |||
| ) | [static] |
getNumOfConsecutiveZeros - Return the number of elements in a result of a shuffle that is zero.
Definition at line 3120 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getShuffleScalarElt(), Idx, Index, isZeroNode(), and llvm::ISD::UNDEF.
Referenced by isVectorShift().
| static SDValue getOnesVector | ( | MVT | VT, | |
| SelectionDAG & | DAG | |||
| ) | [static] |
getOnesVector - Returns a vector of specified type with all bits set.
Definition at line 2921 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::MVT::isVector(), llvm::MVT::v2i32, and llvm::MVT::v4i32.
| static SDValue getShuffleVectorZeroOrUndef | ( | SDValue | V2, | |
| unsigned | Idx, | |||
| bool | isZero, | |||
| bool | HasSSE2, | |||
| SelectionDAG & | DAG | |||
| ) | [static] |
getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified vector of zero or undef vector. This produces a shuffle where the low element of V2 is swizzled into the zero/undef vector, landing at element Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
Definition at line 3097 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), getZeroVector(), llvm::SmallVectorImpl< T >::push_back(), llvm::SmallVectorImpl< T >::size(), llvm::ISD::UNDEF, V1, and llvm::ISD::VECTOR_SHUFFLE.
getSplatMaskEltNo - Given a splat mask, return the index to the element we want to splat.
Definition at line 2564 of file X86ISelLowering.cpp.
References llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), and llvm::X86::isSplatMask().
Referenced by PromoteSplat().
| static SDValue getSwapEltZeroMask | ( | unsigned | NumElems, | |
| unsigned | DestElt, | |||
| SelectionDAG & | DAG | |||
| ) | [static] |
getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps element #0 of a vector with the specified index, leaving the rest of the elements in place.
Definition at line 3005 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().
| static SDValue getUnpackhMask | ( | unsigned | NumElems, | |
| SelectionDAG & | DAG | |||
| ) | [static] |
getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation of specified width.
Definition at line 2990 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().
Referenced by PromoteSplat().
| static SDValue getUnpacklMask | ( | unsigned | NumElems, | |
| SelectionDAG & | DAG | |||
| ) | [static] |
getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation of specified width.
Definition at line 2977 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().
Referenced by PromoteSplat().
| static SDValue getVShift | ( | bool | isLeft, | |
| MVT | VT, | |||
| SDValue | SrcOp, | |||
| unsigned | NumBits, | |||
| SelectionDAG & | DAG, | |||
| const TargetLowering & | TLI | |||
| ) | [static] |
getVShift - Return a vector logical shift node.
Definition at line 3255 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::getShiftAmountTy(), llvm::MVT::getSizeInBits(), llvm::MVT::v1i64, llvm::MVT::v2i64, llvm::X86ISD::VSHL, and llvm::X86ISD::VSRL.
| static SDValue getVZextMovL | ( | MVT | VT, | |
| MVT | OpVT, | |||
| SDValue | SrcOp, | |||
| SelectionDAG & | DAG, | |||
| const X86Subtarget * | Subtarget | |||
| ) | [static] |
getVZextMovL - Return a zero-extending vector move low node.
Definition at line 3824 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), isScalarLoadToVector(), llvm::ISD::SCALAR_TO_VECTOR, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::X86ISD::VZEXT_MOVL.
| static SDValue getZeroVector | ( | MVT | VT, | |
| bool | HasSSE2, | |||
| SelectionDAG & | DAG | |||
| ) | [static] |
getZeroVector - Returns a vector of specified type with all zero elements.
Definition at line 2900 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::ISD::BUILD_VECTOR, llvm::MVT::f32, llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetConstantFP(), llvm::MVT::i32, llvm::MVT::isVector(), llvm::MVT::v2i32, llvm::MVT::v4f32, and llvm::MVT::v4i32.
Referenced by getShuffleVectorZeroOrUndef(), LowerBuildVectorv16i8(), and LowerBuildVectorv8i16().
| static bool hasFPCMov | ( | unsigned | X86CC | ) | [static] |
hasFPCMov - is there a floating point cmov for the specific X86 condition code. Current x86 isa includes the following FP cmov instructions: fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
Definition at line 2073 of file X86ISelLowering.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::X86::COND_NP, and llvm::X86::COND_P.
Definition at line 5359 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::OR, and llvm::X86ISD::SETCC.
| static bool isBaseAlignmentOfN | ( | unsigned | N, | |
| SDNode * | Base, | |||
| const TargetLowering & | TLI | |||
| ) | [static] |
Definition at line 7547 of file X86ISelLowering.cpp.
References llvm::GlobalValue::getAlignment(), and llvm::TargetLowering::isGAPlusOffset().
Referenced by PerformShuffleCombine().
| static bool isCommutedMOVL | ( | SDNode * | N, | |
| bool | V2IsSplat = false, |
|||
| bool | V2IsUndef = false | |||
| ) | [static] |
Definition at line 2451 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), isCommutedMOVL(), and llvm::SDNode::op_begin().
| static bool isCommutedMOVL | ( | SDOperand * | Ops, | |
| unsigned | NumOps, | |||
| bool | V2IsSplat = false, |
|||
| bool | V2IsUndef = false | |||
| ) | [inline, static] |
isCommutedMOVL - Returns true if the shuffle mask is except the reverse of what x86 movss want. X86 movs requires the lowest element to be lowest element of vector 2 and the other elements to come from vector 1 in order.
Definition at line 2431 of file X86ISelLowering.cpp.
References isUndefOrEqual(), and isUndefOrInRange().
Referenced by isCommutedMOVL(), and llvm::X86TargetLowering::isVectorClearMaskLegal().
| static bool isCommutedSHUFP | ( | SDNode * | N | ) | [static] |
Definition at line 2218 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), isCommutedSHUFP(), and llvm::SDNode::op_begin().
| static bool isCommutedSHUFP | ( | SDOperand * | Ops, | |
| unsigned | NumOps | |||
| ) | [inline, static] |
isCommutedSHUFP - Returns true if the shuffle mask is exactly the reverse of what x86 shuffles want. x86 shuffles requires the lower half elements to come from vector 1 (which would equal the dest.) and the upper half to come from vector 2.
Definition at line 2205 of file X86ISelLowering.cpp.
References isUndefOrInRange().
Referenced by isCommutedSHUFP(), and llvm::X86TargetLowering::isVectorClearMaskLegal().
| static bool isIdentityMask | ( | SDNode * | N, | |
| bool | RHS = false | |||
| ) | [static] |
isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand specifies a identity operation on the LHS or RHS.
Definition at line 2522 of file X86ISelLowering.cpp.
References llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), isUndefOrEqual(), and RHS.
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
| static bool isMOVLMask | ( | SDOperand * | Elts, | |
| unsigned | NumElts | |||
| ) | [inline, static] |
isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSS, MOVSD, and MOVD, i.e. setting the lowest element.
Definition at line 2407 of file X86ISelLowering.cpp.
References isUndefOrEqual().
Referenced by llvm::X86::isMOVLMask(), and llvm::X86TargetLowering::isVectorClearMaskLegal().
| static bool isPSHUFHW_PSHUFLWMask | ( | SDNode * | N | ) | [static] |
isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand specifies a 8 element shuffle that can be broken into a pair of PSHUFHW and PSHUFLW.
Definition at line 2678 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
| static bool isScalarLoadToVector | ( | SDNode * | N, | |
| LoadSDNode ** | LD = NULL | |||
| ) | [static] |
isScalarLoadToVector - Returns true if the node is a scalar load that is promoted to a vector. It also returns the LoadSDNode by reference if required.
Definition at line 2782 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isNON_EXTLoad(), and llvm::ISD::SCALAR_TO_VECTOR.
Referenced by getVZextMovL(), and ShouldXformToMOVLP().
| static bool isSHUFPMask | ( | SDOperand * | Elems, | |
| unsigned | NumElems | |||
| ) | [inline, static] |
isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to SHUFP*.
Definition at line 2181 of file X86ISelLowering.cpp.
References isUndefOrInRange().
Referenced by llvm::X86::isSHUFPMask(), and llvm::X86TargetLowering::isVectorClearMaskLegal().
| static bool isSplatMask | ( | SDNode * | N | ) | [static] |
isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element.
Definition at line 2532 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal(), llvm::X86::isSplatMask(), and PerformShiftCombine().
| static bool isSplatVector | ( | SDNode * | N | ) | [static] |
isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are all the same.
Definition at line 2820 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), and llvm::SDNode::getOperand().
isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return true if Op is undef or if its value equal to the specified value.
Definition at line 2101 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), and llvm::ISD::UNDEF.
Referenced by isCommutedMOVL(), isIdentityMask(), llvm::X86::isMOVDDUPMask(), llvm::X86::isMOVHLPS_v_undef_Mask(), llvm::X86::isMOVHLPSMask(), llvm::X86::isMOVHPMask(), isMOVLMask(), llvm::X86::isMOVLPMask(), llvm::X86::isPSHUFLWMask(), llvm::X86::isSplatLoMask(), llvm::X86::isUNPCKH_v_undef_Mask(), isUNPCKHMask(), llvm::X86::isUNPCKL_v_undef_Mask(), isUNPCKLMask(), ShouldXformToMOVHLPS(), and ShouldXformToMOVLP().
isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return true if Op is undef or if its value falls within the specified range (L, H].
Definition at line 2091 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), and llvm::ISD::UNDEF.
Referenced by isCommutedMOVL(), isCommutedSHUFP(), llvm::X86::isPSHUFLWMask(), and isSHUFPMask().
| static bool isUndefShuffle | ( | SDNode * | N | ) | [static] |
isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved to an undef.
Definition at line 2833 of file X86ISelLowering.cpp.
References llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ISD::UNDEF, V1, and llvm::ISD::VECTOR_SHUFFLE.
| static bool isUNPCKHMask | ( | SDOperand * | Elts, | |
| unsigned | NumElts, | |||
| bool | V2IsSplat = false | |||
| ) | [inline, static] |
isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKH.
Definition at line 2330 of file X86ISelLowering.cpp.
References isUndefOrEqual().
Referenced by llvm::X86::isUNPCKHMask().
| static bool isUNPCKLMask | ( | SDOperand * | Elts, | |
| unsigned | NumElts, | |||
| bool | V2IsSplat = false | |||
| ) | [inline, static] |
isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKL.
Definition at line 2300 of file X86ISelLowering.cpp.
References isUndefOrEqual().
Referenced by llvm::X86::isUNPCKLMask().
| static bool isVectorLoad | ( | SDValue | Op | ) | [static] |
isVectorLoad - Returns true if the node is a vector load, a scalar load that's promoted to vector, or a load bitcasted.
Definition at line 3055 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::isVector(), and llvm::ISD::SCALAR_TO_VECTOR.
Referenced by CanonicalizeMovddup().
| static bool isVectorShift | ( | SDValue | Op, | |
| SDValue | Mask, | |||
| SelectionDAG & | DAG, | |||
| bool & | isLeft, | |||
| SDValue & | ShVal, | |||
| unsigned & | ShAmt | |||
| ) | [static] |
isVectorShift - Returns true if the shuffle can be implemented as a logical left or right shift of a vector.
Definition at line 3142 of file X86ISelLowering.cpp.
References getNumOfConsecutiveZeros(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOperand(), Idx, Index, and llvm::ISD::UNDEF.
| static bool isX86LogicalCmp | ( | unsigned | Opc | ) | [static] |
Definition at line 5307 of file X86ISelLowering.cpp.
References llvm::X86ISD::CMP, llvm::X86ISD::COMI, and llvm::X86ISD::UCOMI.
| static bool isXor1OfSetCC | ( | SDValue | Op | ) | [static] |
Definition at line 5371 of file X86ISelLowering.cpp.
References llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::X86ISD::SETCC, and llvm::ISD::XOR.
| static bool isZeroNode | ( | SDValue | Elt | ) | [inline, static] |
isZeroNode - Returns true if Elt is a constant zero or a floating point constant +0.0.
Definition at line 2856 of file X86ISelLowering.cpp.
Referenced by getNumOfConsecutiveZeros(), isZeroShuffle(), and PerformBuildVectorCombine().
| static bool isZeroShuffle | ( | SDNode * | N | ) | [static] |
isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved to an zero vector.
Definition at line 2865 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDValue::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), Idx, llvm::ISD::isBuildVectorAllZeros(), isZeroNode(), llvm::ISD::UNDEF, V1, and llvm::ISD::VECTOR_SHUFFLE.
| static SDValue LowerBuildVectorv16i8 | ( | SDValue | Op, | |
| unsigned | NonZeros, | |||
| unsigned | NumNonZero, | |||
| unsigned | NumZero, | |||
| SelectionDAG & | DAG, | |||
| TargetLowering & | TLI | |||
| ) | [static] |
LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
Definition at line 3183 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), getZeroVector(), llvm::MVT::i16, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::UNDEF, V, llvm::MVT::v16i8, llvm::MVT::v8i16, and llvm::ISD::ZERO_EXTEND.
| static SDValue LowerBuildVectorv8i16 | ( | SDValue | Op, | |
| unsigned | NonZeros, | |||
| unsigned | NumNonZero, | |||
| unsigned | NumZero, | |||
| SelectionDAG & | DAG, | |||
| TargetLowering & | TLI | |||
| ) | [static] |
LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
Definition at line 3227 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), getZeroVector(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::UNDEF, V, and llvm::MVT::v8i16.
| static SDValue LowerToTLSExecModel | ( | GlobalAddressSDNode * | GA, | |
| SelectionDAG & | DAG, | |||
| const MVT | PtrVT | |||
| ) | [static] |
Definition at line 4600 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SelectionDAG::getEntryNode(), llvm::GlobalAddressSDNode::getGlobal(), llvm::PseudoSourceValue::getGOT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDNode::getValueType(), llvm::GlobalValue::isDeclaration(), llvm::X86ISD::THREAD_POINTER, and llvm::X86ISD::Wrapper.
| static SDValue LowerToTLSGeneralDynamicModel32 | ( | GlobalAddressSDNode * | GA, | |
| SelectionDAG & | DAG, | |||
| const MVT | PtrVT | |||
| ) | [static] |
Definition at line 4529 of file X86ISelLowering.cpp.
References llvm::X86ISD::CALL, llvm::N86::EAX, llvm::N86::EBX, llvm::MVT::Flag, llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::X86ISD::GlobalBaseReg, llvm::MVT::Other, and llvm::X86ISD::TLSADDR.
| static SDValue LowerToTLSGeneralDynamicModel64 | ( | GlobalAddressSDNode * | GA, | |
| SelectionDAG & | DAG, | |||
| const MVT | PtrVT | |||
| ) | [static] |
Definition at line 4567 of file X86ISelLowering.cpp.
References llvm::X86ISD::CALL, llvm::MVT::Flag, llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Other, and llvm::X86ISD::TLSADDR.
| static SDValue LowerVECTOR_SHUFFLE_4wide | ( | SDValue | V1, | |
| SDValue | V2, | |||
| SDValue | PermMask, | |||
| MVT | VT, | |||
| SelectionDAG & | DAG | |||
| ) | [static] |
LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of shuffles.
Definition at line 3858 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SmallVectorImpl< T >::clear(), CommuteVectorShuffleMask(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), llvm::SmallVectorImpl< T >::resize(), llvm::SmallVectorImpl< T >::size(), std::swap(), llvm::ISD::UNDEF, and llvm::ISD::VECTOR_SHUFFLE.
| static SDValue LowerVECTOR_SHUFFLEv8i16 | ( | SDValue | V1, | |
| SDValue | V2, | |||
| SDValue | PermMask, | |||
| SelectionDAG & | DAG, | |||
| TargetLowering & | TLI | |||
| ) | [static] |
Definition at line 3511 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::ISD::BUILD_VECTOR, llvm::SmallVectorImpl< T >::clear(), CommuteVectorShuffleMask(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::TargetLowering::getPointerTy(), llvm::MVT::getVectorElementType(), llvm::MVT::i16, llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::SmallVectorImpl< T >::push_back(), llvm::BitVector::set(), std::swap(), llvm::ISD::UNDEF, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v8i16, and llvm::ISD::VECTOR_SHUFFLE.
| static SDValue NormalizeMask | ( | SDValue | Mask, | |
| SelectionDAG & | DAG | |||
| ) | [static] |
NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements that point to V2 points to its first element.
Definition at line 2938 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, Changed, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SmallVectorImpl< T >::push_back(), llvm::SmallVectorImpl< T >::size(), and llvm::ISD::UNDEF.
| static SDValue PerformBTCombine | ( | SDNode * | N, | |
| SelectionDAG & | DAG, | |||
| TargetLowering::DAGCombinerInfo & | DCI | |||
| ) | [static] |
Definition at line 7953 of file X86ISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::APInt::getLowBitsSet(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::hasOneUse(), llvm::Log2_32(), llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(), llvm::TargetLowering::SimplifyDemandedBits(), and TLI.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
| static SDValue PerformBuildVectorCombine | ( | SDNode * | N, | |
| SelectionDAG & | DAG, | |||
| TargetLowering::DAGCombinerInfo & | DCI, | |||
| const X86Subtarget * | Subtarget, | |||
| const TargetLowering & | TLI | |||
| ) | [static] |
PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
Definition at line 7617 of file X86ISelLowering.cpp.
References Base, llvm::ISD::BIT_CONVERT, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::MVT::f64, llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::X86Subtarget::is64Bit(), llvm::TargetLowering::isTypeLegal(), isZeroNode(), llvm::ISD::NON_EXTLOAD, llvm::MVT::Other, and llvm::X86ISD::VZEXT_LOAD.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
| static SDValue PerformFANDCombine | ( | SDNode * | N, | |
| SelectionDAG & | DAG | |||
| ) | [static] |
PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
Definition at line 7941 of file X86ISelLowering.cpp.
References llvm::SDNode::getOperand().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
| static SDValue PerformFORCombine | ( | SDNode * | N, | |
| SelectionDAG & | DAG | |||
| ) | [static] |
PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
Definition at line 7927 of file X86ISelLowering.cpp.
References llvm::X86ISD::FOR, llvm::X86ISD::FXOR, llvm::SDNode::getOpcode(), and llvm::SDNode::getOperand().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
| static SDValue PerformSELECTCombine | ( | SDNode * | N, | |
| SelectionDAG & | DAG, | |||
| const X86Subtarget * | Subtarget | |||
| ) | [static] |
PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
Definition at line 7670 of file X86ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::X86ISD::FMAX, llvm::X86ISD::FMIN, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::X86Subtarget::hasSSE2(), llvm::ISD::SETCC, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::UnsafeFPMath.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
| static SDValue PerformShiftCombine | ( | SDNode * | N, | |
| SelectionDAG & | DAG, | |||
| const X86Subtarget * | Subtarget | |||
| ) | [static] |
PerformShiftCombine - Transforms vector shift nodes to use vector shifts when possible.
Definition at line 7743 of file X86ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::MVT::bitsGT(), llvm::MVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, isSplatMask(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::ISD::UNDEF, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::ISD::VECTOR_SHUFFLE, llvm::Intrinsic::x86_sse2_pslli_d, llvm::Intrinsic::x86_sse2_pslli_q, llvm::Intrinsic::x86_sse2_pslli_w, llvm::Intrinsic::x86_sse2_psrai_d, llvm::Intrinsic::x86_sse2_psrai_w, llvm::Intrinsic::x86_sse2_psrli_d, llvm::Intrinsic::x86_sse2_psrli_q, and llvm::Intrinsic::x86_sse2_psrli_w.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
| static SDValue PerformShuffleCombine | ( | SDNode * | N, | |
| SelectionDAG & | DAG, | |||
| const TargetLowering & | TLI | |||
| ) | [static] |
PerformShuffleCombine - Combine a vector_shuffle that is equal to build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are consecutive, non-overlapping, and in the right order.
Definition at line 7595 of file X86ISelLowering.cpp.
References Base, EltsFromConsecutiveLoads(), llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SDValue::getNumOperands(), llvm::SDNode::getOperand(), llvm::MemSDNode::getSrcValue(), llvm::MemSDNode::getSrcValueOffset(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), isBaseAlignmentOfN(), and llvm::MemSDNode::isVolatile().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
| static SDValue PerformSTORECombine | ( | SDNode * | N, | |
| SelectionDAG & | DAG, | |||
| const X86Subtarget * | Subtarget | |||
| ) | [static] |
PerformSTORECombine - Do target-specific dag combines on STORE nodes.
Definition at line 7836 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MVT::getSizeInBits(), llvm::MemSDNode::getSrcValue(), llvm::MemSDNode::getSrcValueOffset(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::X86Subtarget::is64Bit(), llvm::MVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::MinAlign(), llvm::MVT::Other, llvm::SmallVectorImpl< T >::push_back(), llvm::SmallVectorImpl< T >::size(), and llvm::ISD::TokenFactor.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
| static SDValue PromoteSplat | ( | SDValue | Op, | |
| SelectionDAG & | DAG, | |||
| bool | HasSSE2 | |||
| ) | [static] |
PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
Definition at line 3018 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOperand(), getSplatMaskEltNo(), getUnpackhMask(), getUnpacklMask(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::ISD::UNDEF, V1, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::ISD::VECTOR_SHUFFLE.
| static SDValue RewriteAsNarrowerShuffle | ( | SDValue | V1, | |
| SDValue | V2, | |||
| MVT | VT, | |||
| SDValue | PermMask, | |||
| SelectionDAG & | DAG, | |||
| TargetLowering & | TLI | |||
| ) | [static] |
RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be done when every pair / quad of shuffle mask elements point to elements in the right sequence. e.g. vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
Definition at line 3772 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getSimpleVT(), llvm::MVT::getVectorElementType(), llvm::MVT::isInteger(), llvm::SmallVectorImpl< T >::push_back(), Scale, llvm::SmallVectorImpl< T >::size(), llvm::ISD::UNDEF, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8i16, and llvm::ISD::VECTOR_SHUFFLE.
| static bool ShouldXformToMOVHLPS | ( | SDNode * | Mask | ) | [static] |
ShouldXformToMOVHLPS - Return true if the node should be transformed to match movhlps. The lower half elements should come from upper half of V1 (and in order), and the upper half elements should come from the upper half of V2 (and in order).
Definition at line 2766 of file X86ISelLowering.cpp.
References llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), and isUndefOrEqual().
ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to match movlp{s|d}. The lower half elements should come from lower half of V1 (and in order), and the upper half elements should come from the upper half of V2 (and in order). And since V1 will become the source of the MOVLP, it must be either a vector load or a scalar load to vector.
Definition at line 2798 of file X86ISelLowering.cpp.
References llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::ISD::isNON_EXTLoad(), isScalarLoadToVector(), and isUndefOrEqual().
| static unsigned TranslateX86CC | ( | ISD::CondCode | SetCCOpcode, | |
| bool | isFP, | |||
| SDValue & | LHS, | |||
| SDValue & | RHS, | |||
| SelectionDAG & | DAG | |||
| ) | [static] |
TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 specific condition code, returning the condition code and the LHS/RHS of the comparison to make.
Definition at line 1989 of file X86ISelLowering.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NP, llvm::X86::COND_NS, llvm::X86::COND_P, llvm::X86::COND_S, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::ISD::isNON_EXTLoad(), llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUO, and std::swap().
cl::opt<bool> DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")) [static] |
Referenced by llvm::X86TargetLowering::X86TargetLowering().
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