llvm::ARMInstrInfo Class Reference

#include <ARMInstrInfo.h>

Inheritance diagram for llvm::ARMInstrInfo:

Collaboration diagram for llvm::ARMInstrInfo:

Detailed Description

Definition at line 143 of file ARMInstrInfo.h.

Constructor & Destructor Documentation

ARMInstrInfo::ARMInstrInfo ( const ARMSubtarget & STI ) [explicit]

Definition at line 41 of file ARMInstrInfo.cpp.

Member Function Documentation

virtual const ARMRegisterInfo& llvm::ARMInstrInfo::getRegisterInfo ( ) const [inline, virtual]

getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 152 of file ARMInstrInfo.h.

Referenced by llvm::ARMTargetMachine::getRegisterInfo().

const TargetRegisterClass * ARMInstrInfo::getPointerRegClass ( ) const [virtual]

getPointerRegClass - Return the register class to use to hold pointers. This is used for addressing modes.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 46 of file ARMInstrInfo.cpp.

bool ARMInstrInfo::isMoveInstr	(	const MachineInstr &	MI,
		unsigned &	SrcReg,
		unsigned &	DstReg,
		unsigned &	SrcSubIdx,
		unsigned &	DstSubIdx
	)			const `[virtual]`

Return true if the instruction is a register to register move and return the source and dest operands and their sub-register indices by reference.

Return true if the instruction is a register to register move and leave the source and dest operands in the passed parameters.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 53 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::TargetInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().

unsigned ARMInstrInfo::isLoadFromStackSlot	(	const MachineInstr *	MI,
		int &	FrameIndex
	)			const `[virtual]`

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 79 of file ARMInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().

unsigned ARMInstrInfo::isStoreToStackSlot	(	const MachineInstr *	MI,
		int &	FrameIndex
	)			const `[virtual]`

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 114 of file ARMInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().

void ARMInstrInfo::reMaterialize	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	DestReg,
		const MachineInstr *	Orig
	)			const `[virtual]`

reMaterialize - Re-issue the specified 'original' instruction at the specific location targeting a new destination register.

Reimplemented from llvm::TargetInstrInfoImpl.

Definition at line 149 of file ARMInstrInfo.cpp.

References llvm::MachineFunction::CloneMachineInstr(), llvm::ARMRegisterInfo::emitLoadConstPool(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), MI, and llvm::MachineOperand::setReg().

MachineInstr * ARMInstrInfo::convertToThreeAddress	(	MachineFunction::iterator &	MFI,
		MachineBasicBlock::iterator &	MBBI,
		LiveVariables *	LV
	)			const `[virtual]`

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into one or more true three-address instructions on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.

This method returns a null pointer if the transformation cannot be performed, otherwise it returns the last new instruction.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 197 of file ARMInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), AddrMode, llvm::ARMII::AddrMode2, llvm::ARMII::AddrMode3, llvm::ARMII::AddrModeMask, llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), Base, BaseReg, llvm::BuildMI(), EnableARM3Addr, llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::TargetInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getSORegOpc(), getUnindexedOpcode(), llvm::LiveVariables::getVarInfo(), llvm::ARMII::IndexModeMask, llvm::ARMII::IndexModePost, llvm::ARMII::IndexModePre, llvm::ARMII::IndexModeShift, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::LiveVariables::VarInfo::Kills, llvm::TargetInstrDesc::mayStore(), MF, MI, Offset, Pred, llvm::MachineInstr::readsRegister(), Reg, llvm::LiveVariables::VarInfo::removeKill(), llvm::MachineOperand::setIsDead(), llvm::ARM_AM::sub, and llvm::TargetInstrDesc::TSFlags.

bool ARMInstrInfo::AnalyzeBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify
	)			const `[virtual]`

AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:

1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null. 2. If this block ends with only an unconditional branch, it sets TBB to be the destination block. 3. If this block ends with an conditional branch and it falls through to an successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. 4. If this block ends with an conditional branch and an unconditional block, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.

Note that RemoveBranch and InsertBranch must be implemented to support cases where this method returns success.

If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).

Reimplemented from llvm::TargetInstrInfo.

Definition at line 339 of file ARMInstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), and llvm::SmallVectorImpl< T >::push_back().

unsigned ARMInstrInfo::RemoveBranch ( MachineBasicBlock & MBB ) const [virtual]

RemoveBranch - Remove the branching code at the end of the specific MBB. This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions that were removed.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 414 of file ARMInstrInfo.cpp.

References AFI, llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::ARMFunctionInfo::isThumbFunction(), and MF.

unsigned ARMInstrInfo::InsertBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *	TBB,
		MachineBasicBlock *	FBB,
		const SmallVectorImpl< MachineOperand > &	Cond
	)			const `[virtual]`

InsertBranch - Insert a branch into the end of the specified MachineBasicBlock. This operands to this method are the same as those returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch returns success and when an unconditional branch (TBB is non-null, FBB is null, Cond is empty) needs to be inserted. It returns the number of instructions inserted.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 441 of file ARMInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), AFI, llvm::BuildMI(), llvm::SmallVectorImpl< T >::empty(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::ARMFunctionInfo::isThumbFunction(), MF, and llvm::SmallVectorImpl< T >::size().

bool ARMInstrInfo::copyRegToReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	DestReg,
		unsigned	SrcReg,
		const TargetRegisterClass *	DestRC,
		const TargetRegisterClass *	SrcRC
	)			const `[virtual]`

copyRegToReg - Emit instructions to copy between a pair of registers. It returns false if the target does not how to copy between the specified registers.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 470 of file ARMInstrInfo.cpp.

References AddDefaultCC(), AddDefaultPred(), AFI, llvm::BuildMI(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::ARMFunctionInfo::isThumbFunction(), and MF.

void ARMInstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC
	)			const `[virtual]`

storeRegToStackSlot - Store the specified register of the given register class to the specified stack frame index. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 515 of file ARMInstrInfo.cpp.

References AddDefaultPred(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), AFI, llvm::BuildMI(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::ARMFunctionInfo::isThumbFunction(), and MF.

void ARMInstrInfo::storeRegToAddr	(	MachineFunction &	MF,
		unsigned	SrcReg,
		bool	isKill,
		SmallVectorImpl< MachineOperand > &	Addr,
		const TargetRegisterClass *	RC,
		SmallVectorImpl< MachineInstr * > &	NewMIs
	)			const `[virtual]`

storeRegToAddr - Store the specified register of the given register class to the specified address. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 540 of file ARMInstrInfo.cpp.

References AddDefaultPred(), llvm::MachineInstrBuilder::addReg(), AFI, ARMInstrAddOperand(), llvm::BuildMI(), llvm::MachineFunction::getInfo(), llvm::ARMFunctionInfo::isThumbFunction(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().

void ARMInstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC
	)			const `[virtual]`

loadRegFromStackSlot - Load the specified register of the given register class from the specified stack frame index. The load instruction is to be added to the given machine basic block before the specified machine instruction.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 575 of file ARMInstrInfo.cpp.

References AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), AFI, llvm::BuildMI(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::ARMFunctionInfo::isThumbFunction(), and MF.

void ARMInstrInfo::loadRegFromAddr	(	MachineFunction &	MF,
		unsigned	DestReg,
		SmallVectorImpl< MachineOperand > &	Addr,
		const TargetRegisterClass *	RC,
		SmallVectorImpl< MachineInstr * > &	NewMIs
	)			const `[virtual]`

loadRegFromAddr - Load the specified register of the given register class class from the specified address. The load instruction is to be added to the given machine basic block before the specified machine instruction.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 597 of file ARMInstrInfo.cpp.

References AddDefaultPred(), AFI, ARMInstrAddOperand(), llvm::BuildMI(), llvm::MachineFunction::getInfo(), llvm::ARMFunctionInfo::isThumbFunction(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().

bool ARMInstrInfo::spillCalleeSavedRegisters	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const std::vector< CalleeSavedInfo > &	CSI
	)			const `[virtual]`

spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns true if it isn't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot(). Returns false otherwise.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 628 of file ARMInstrInfo.cpp.

References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), AFI, llvm::BuildMI(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::ARMFunctionInfo::isThumbFunction(), MF, and Reg.

bool ARMInstrInfo::restoreCalleeSavedRegisters	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const std::vector< CalleeSavedInfo > &	CSI
	)			const `[virtual]`

restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns true if it isn't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot(). Returns false otherwise.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 646 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::addOperand(), AFI, llvm::MachineFunction::CreateMachineInstr(), llvm::MachineOperand::CreateReg(), llvm::MachineBasicBlock::erase(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::ARMFunctionInfo::getVarArgsRegSaveSize(), llvm::MachineBasicBlock::insert(), llvm::ARMFunctionInfo::isThumbFunction(), MF, Reg, and llvm::MachineInstr::setDesc().

MachineInstr * ARMInstrInfo::foldMemoryOperandImpl	(	MachineFunction &	MF,
		MachineInstr *	MI,
		const SmallVectorImpl< unsigned > &	Ops,
		int	FrameIndex
	)			const `[virtual]`

foldMemoryOperandImpl - Target-dependent implementation for foldMemoryOperand. Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 672 of file ARMInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), llvm::ARMRegisterInfo::isLowRegister(), Pred, and llvm::SmallVectorImpl< T >::size().

virtual MachineInstr* llvm::ARMInstrInfo::foldMemoryOperandImpl	(	MachineFunction &	MF,
		MachineInstr *	MI,
		const SmallVectorImpl< unsigned > &	Ops,
		MachineInstr *	LoadMI
	)			const `[inline, virtual]`

foldMemoryOperandImpl - Target-dependent implementation for foldMemoryOperand. Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 221 of file ARMInstrInfo.h.

bool ARMInstrInfo::canFoldMemoryOperand	(	const MachineInstr *	MI,
		const SmallVectorImpl< unsigned > &	Ops
	)			const `[virtual]`

canFoldMemoryOperand - Returns true for the specified load / store if folding is possible.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 758 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::ARMRegisterInfo::isLowRegister(), and llvm::SmallVectorImpl< T >::size().

bool ARMInstrInfo::BlockHasNoFallThrough ( const MachineBasicBlock & MBB ) const [virtual]

BlockHasNoFallThrough - Return true if the specified block does not fall-through into its successor block. This is primarily used when a branch is unanalyzable. It is useful for things like unconditional indirect branches (jump tables).

Reimplemented from llvm::TargetInstrInfo.

Definition at line 791 of file ARMInstrInfo.cpp.

References llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::empty(), and llvm::MachineInstr::getOpcode().

bool ARMInstrInfo::ReverseBranchCondition ( SmallVectorImpl< MachineOperand > & Cond ) const [virtual]

ReverseBranchCondition - Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 812 of file ARMInstrInfo.cpp.

References llvm::ARMCC::getOppositeCondition().

bool ARMInstrInfo::isPredicated ( const MachineInstr * MI ) const [virtual]

isPredicated - Returns true if the instruction is already predicated.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 818 of file ARMInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineOperand::getImm(), and llvm::MachineInstr::getOperand().

ARMCC::CondCodes llvm::ARMInstrInfo::getPredicate ( const MachineInstr * MI ) const [inline]

Definition at line 238 of file ARMInstrInfo.h.

References llvm::ARMCC::AL, llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineOperand::getImm(), and llvm::MachineInstr::getOperand().

bool ARMInstrInfo::PredicateInstruction	(	MachineInstr *	MI,
		const SmallVectorImpl< MachineOperand > &	Pred
	)			const `[virtual]`

PredicateInstruction - Convert the instruction into a predicated instruction. It returns true if the operation was successful.

Reimplemented from llvm::TargetInstrInfoImpl.

Definition at line 823 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::addOperand(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().

bool ARMInstrInfo::SubsumesPredicate	(	const SmallVectorImpl< MachineOperand > &	Pred1,
		const SmallVectorImpl< MachineOperand > &	Pred2
	)			const `[virtual]`

SubsumesPredicate - Returns true if the first specified predicate subsumes the second, e.g. GE subsumes GT.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 844 of file ARMInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::SmallVectorImpl< T >::size().

bool ARMInstrInfo::DefinesPredicate	(	MachineInstr *	MI,
		std::vector< MachineOperand > &	Pred
	)			const `[virtual]`

DefinesPredicate - If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 870 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::TargetInstrDesc::getImplicitDefs(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::TargetInstrDesc::hasOptionalDef(), and llvm::MachineOperand::isReg().

unsigned ARMInstrInfo::GetInstSizeInBytes ( const MachineInstr * MI ) const [virtual]

GetInstSize - Returns the size of the specified MachineInstr.

GetInstSize - Return the size of the specified MachineInstr.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 899 of file ARMInstrInfo.cpp.

References llvm::TargetInstrInfo::DBG_LABEL, llvm::TargetInstrInfo::DECLARE, llvm::TargetInstrInfo::EH_LABEL, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::TargetAsmInfo::getInlineAsmLength(), llvm::MachineFunction::getJumpTableInfo(), llvm::MachineJumpTableInfo::getJumpTables(), getNumJTEntries(), llvm::TargetInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::getTargetAsmInfo(), llvm::TargetInstrInfo::IMPLICIT_DEF, llvm::ISD::INLINEASM, llvm::MachineInstr::isLabel(), llvm::TargetInstrDesc::isPredicable(), JT, JTI, MBB, MF, llvm::ARMII::Size2Bytes, llvm::ARMII::Size4Bytes, llvm::ARMII::Size8Bytes, llvm::ARMII::SizeMask, llvm::ARMII::SizeShift, llvm::ARMII::SizeSpecial, and llvm::TargetInstrDesc::TSFlags.

The documentation for this class was generated from the following files:


Public Member Functions
	ARMInstrInfo (const ARMSubtarget &STI)
virtual const ARMRegisterInfo &	getRegisterInfo () const
virtual const TargetRegisterClass *	getPointerRegClass () const
virtual bool	isMoveInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SrcSubIdx, unsigned &DstSubIdx) const
virtual unsigned	isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const
virtual unsigned	isStoreToStackSlot (const MachineInstr *MI, int &FrameIndex) const
void	reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const
virtual MachineInstr *	convertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const
virtual bool	AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
virtual unsigned	RemoveBranch (MachineBasicBlock &MBB) const
virtual unsigned	InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, const SmallVectorImpl< MachineOperand > &Cond) const
virtual bool	copyRegToReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass DestRC, const TargetRegisterClass SrcRC) const
virtual void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC) const
virtual void	storeRegToAddr (MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass RC, SmallVectorImpl< MachineInstr > &NewMIs) const
virtual void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC) const
virtual void	loadRegFromAddr (MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass RC, SmallVectorImpl< MachineInstr > &NewMIs) const
virtual bool	spillCalleeSavedRegisters (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI) const
virtual bool	restoreCalleeSavedRegisters (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI) const
virtual MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const
virtual MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr LoadMI) const
virtual bool	canFoldMemoryOperand (const MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops) const
virtual bool	BlockHasNoFallThrough (const MachineBasicBlock &MBB) const
virtual bool	ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const
virtual bool	isPredicated (const MachineInstr *MI) const
ARMCC::CondCodes	getPredicate (const MachineInstr *MI) const
virtual bool	PredicateInstruction (MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const
virtual bool	SubsumesPredicate (const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const
virtual bool	DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const
virtual unsigned	GetInstSizeInBytes (const MachineInstr *MI) const

llvm::ARMInstrInfo Class Reference

Public Member Functions

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation