1.5.6Copyright © 2003-2007 University of Illinois at Urbana-Champaign. All Rights Reserved.
LLVM API Documentation
#include <ARMISelLowering.h>
Definition at line 73 of file ARMISelLowering.h.
| ARMTargetLowering::ARMTargetLowering | ( | TargetMachine & | TM | ) | [explicit] |
Definition at line 39 of file ARMISelLowering.cpp.
References llvm::RTLIB::ADD_F32, llvm::RTLIB::ADD_F64, llvm::TargetLowering::addRegisterClass(), llvm::ISD::BIT_CONVERT, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::TargetLowering::computeRegisterProperties(), llvm::ISD::ConstantPool, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::TargetLowering::Custom, llvm::ISD::DBG_STOPPOINT, llvm::ISD::DEBUG_LOC, llvm::RTLIB::DIV_F32, llvm::RTLIB::DIV_F64, llvm::ISD::DYNAMIC_STACKALLOC, llvm::TargetLowering::Expand, llvm::ISD::EXTLOAD, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::RTLIB::FPEXT_F32_F64, llvm::ISD::FPOW, llvm::RTLIB::FPROUND_F64_F32, llvm::RTLIB::FPTOSINT_F32_I32, llvm::RTLIB::FPTOSINT_F64_I32, llvm::RTLIB::FPTOUINT_F32_I32, llvm::RTLIB::FPTOUINT_F64_I32, llvm::ISD::FREM, llvm::ISD::FSIN, llvm::TargetMachine::getSubtarget(), llvm::ISD::GLOBAL_OFFSET_TABLE, llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ARMSubtarget::hasV5TOps(), llvm::ARMSubtarget::hasV6Ops(), llvm::ARMSubtarget::hasVFP2(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ARMSubtarget::isTargetDarwin(), llvm::ARMSubtarget::isThumb(), llvm::ISD::LAST_INDEXED_MODE, llvm::TargetLowering::Legal, llvm::TargetLowering::maxStoresPerMemcpy, llvm::ISD::MEMBARRIER, llvm::ISD::MUL, llvm::RTLIB::MUL_F32, llvm::RTLIB::MUL_F64, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::RTLIB::O_F32, llvm::RTLIB::O_F64, llvm::RTLIB::OEQ_F32, llvm::RTLIB::OEQ_F64, llvm::RTLIB::OGE_F32, llvm::RTLIB::OGE_F64, llvm::RTLIB::OGT_F32, llvm::RTLIB::OGT_F64, llvm::RTLIB::OLE_F32, llvm::RTLIB::OLE_F64, llvm::RTLIB::OLT_F32, llvm::RTLIB::OLT_F64, llvm::MVT::Other, llvm::ISD::PRE_INC, llvm::TargetLowering::Promote, llvm::ISD::RET, llvm::ISD::ROTL, llvm::TargetLowering::SchedulingForRegPressure, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::TargetLowering::setCmpLibcallCC(), llvm::ISD::SETEQ, llvm::TargetLowering::setIfCvtBlockSizeLimit(), llvm::TargetLowering::setIfCvtDupBlockSizeLimit(), llvm::TargetLowering::setIndexedLoadAction(), llvm::TargetLowering::setIndexedStoreAction(), llvm::TargetLowering::setLibcallName(), llvm::TargetLowering::setLoadExtAction(), llvm::ISD::SETNE, llvm::TargetLowering::setOperationAction(), llvm::TargetLowering::setSchedulingPreference(), llvm::TargetLowering::setStackPointerRegisterToSaveRestore(), llvm::TargetLowering::setTruncStoreAction(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::RTLIB::SINTTOFP_I32_F32, llvm::RTLIB::SINTTOFP_I32_F64, llvm::ISD::SMUL_LOHI, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::RTLIB::SUB_F32, llvm::RTLIB::SUB_F64, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::RTLIB::UINTTOFP_I32_F32, llvm::RTLIB::UINTTOFP_I32_F64, llvm::ISD::UMUL_LOHI, llvm::RTLIB::UNE_F32, llvm::RTLIB::UNE_F64, llvm::RTLIB::UO_F32, llvm::RTLIB::UO_F64, llvm::ISD::UREM, llvm::UseSoftFloat, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, and llvm::ISD::VASTART.
| SDValue ARMTargetLowering::LowerOperation | ( | SDValue | Op, | |
| SelectionDAG & | DAG | |||
| ) | [virtual] |
LowerOperation - This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.
Reimplemented from llvm::TargetLowering.
Definition at line 1403 of file ARMISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::CALL, llvm::ISD::ConstantPool, ExpandBIT_CONVERT(), ExpandSRx(), llvm::ISD::FCOPYSIGN, llvm::ISD::FORMAL_ARGUMENTS, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRAMEADDR, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::ISD::GLOBAL_OFFSET_TABLE, llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ARMSubtarget::isTargetDarwin(), LowerBR_CC(), LowerConstantPool(), LowerFCOPYSIGN(), LowerFP_TO_INT(), LowerINT_TO_FP(), LowerINTRINSIC_WO_CHAIN(), LowerRET(), LowerSELECT_CC(), LowerVASTART(), llvm::ISD::RET, llvm::ISD::RETURNADDR, llvm::ISD::SELECT_CC, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::UINT_TO_FP, and llvm::ISD::VASTART.
| void ARMTargetLowering::ReplaceNodeResults | ( | SDNode * | N, | |
| SmallVectorImpl< SDValue > & | Results, | |||
| SelectionDAG & | DAG | |||
| ) | [virtual] |
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.
Reimplemented from llvm::TargetLowering.
Definition at line 1438 of file ARMISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, ExpandBIT_CONVERT(), ExpandSRx(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SmallVectorImpl< T >::push_back(), llvm::ISD::SRA, and llvm::ISD::SRL.
| SDValue ARMTargetLowering::PerformDAGCombine | ( | SDNode * | N, | |
| DAGCombinerInfo & | DCI | |||
| ) | const [virtual] |
PerformDAGCombine - This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Reimplemented from llvm::TargetLowering.
Definition at line 1540 of file ARMISelLowering.cpp.
References llvm::ARMISD::FMRRD, llvm::SDNode::getOpcode(), and PerformFMRRDCombine().
| const char * ARMTargetLowering::getTargetNodeName | ( | unsigned | Opcode | ) | const [virtual] |
getTargetNodeName() - This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 269 of file ARMISelLowering.cpp.
References llvm::ARMISD::BR_JT, llvm::ARMISD::BRCOND, llvm::ARMISD::CALL, llvm::ARMISD::CALL_NOLINK, llvm::ARMISD::CALL_PRED, llvm::ARMISD::CMOV, llvm::ARMISD::CMP, llvm::ARMISD::CMPFP, llvm::ARMISD::CMPFPw0, llvm::ARMISD::CMPNZ, llvm::ARMISD::CNEG, llvm::ARMISD::FMDRR, llvm::ARMISD::FMRRD, llvm::ARMISD::FMSTAT, llvm::ARMISD::FTOSI, llvm::ARMISD::FTOUI, llvm::ARMISD::PIC_ADD, llvm::ARMISD::RET_FLAG, llvm::ARMISD::RRX, llvm::ARMISD::SITOF, llvm::ARMISD::SRA_FLAG, llvm::ARMISD::SRL_FLAG, llvm::ARMISD::tCALL, llvm::ARMISD::THREAD_POINTER, llvm::ARMISD::UITOF, llvm::ARMISD::Wrapper, and llvm::ARMISD::WrapperJT.
| MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter | ( | MachineInstr * | MI, | |
| MachineBasicBlock * | MBB | |||
| ) | [virtual] |
Reimplemented from llvm::TargetLowering.
Definition at line 1464 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineFunction::DeleteMachineInstr(), F, llvm::TargetInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineOperand::getImm(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::TargetLowering::getTargetMachine(), llvm::MachineFunction::insert(), PHI, llvm::MachineBasicBlock::removeSuccessor(), llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_empty(), llvm::MachineBasicBlock::succ_end(), and TII.
| bool ARMTargetLowering::isLegalAddressingMode | ( | const AddrMode & | AM, | |
| const Type * | Ty | |||
| ) | const [virtual] |
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
Reimplemented from llvm::TargetLowering.
Definition at line 1611 of file ARMISelLowering.cpp.
References llvm::TargetLowering::AddrMode::BaseGV, llvm::TargetLowering::AddrMode::BaseOffs, llvm::MVT::getSimpleVT(), llvm::TargetLowering::getValueType(), llvm::TargetLowering::AddrMode::HasBaseReg, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, isLegalAddressImmediate(), llvm::isPowerOf2_32(), llvm::ARMSubtarget::isThumb(), llvm::MVT::isVoid, Scale, and llvm::TargetLowering::AddrMode::Scale.
| bool ARMTargetLowering::getPreIndexedAddressParts | ( | SDNode * | N, | |
| SDValue & | Base, | |||
| SDValue & | Offset, | |||
| ISD::MemIndexedMode & | AM, | |||
| SelectionDAG & | DAG | |||
| ) | const [virtual] |
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.
Reimplemented from llvm::TargetLowering.
Definition at line 1728 of file ARMISelLowering.cpp.
References getIndexedAddressParts(), llvm::SDValue::getNode(), llvm::ISD::isSEXTLoad(), llvm::ARMSubtarget::isThumb(), llvm::ISD::PRE_DEC, llvm::ISD::PRE_INC, and llvm::ISD::SEXTLOAD.
| bool ARMTargetLowering::getPostIndexedAddressParts | ( | SDNode * | N, | |
| SDNode * | Op, | |||
| SDValue & | Base, | |||
| SDValue & | Offset, | |||
| ISD::MemIndexedMode & | AM, | |||
| SelectionDAG & | DAG | |||
| ) | const [virtual] |
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.
Reimplemented from llvm::TargetLowering.
Definition at line 1761 of file ARMISelLowering.cpp.
References getIndexedAddressParts(), llvm::ISD::isSEXTLoad(), llvm::ARMSubtarget::isThumb(), llvm::ISD::POST_DEC, llvm::ISD::POST_INC, and llvm::ISD::SEXTLOAD.
| void ARMTargetLowering::computeMaskedBitsForTargetNode | ( | const SDValue | Op, | |
| const APInt & | Mask, | |||
| APInt & | KnownZero, | |||
| APInt & | KnownOne, | |||
| const SelectionDAG & | DAG, | |||
| unsigned | Depth | |||
| ) | const [virtual] |
computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Reimplemented from llvm::TargetLowering.
Definition at line 1790 of file ARMISelLowering.cpp.
References llvm::ARMISD::CMOV, llvm::SelectionDAG::ComputeMaskedBits(), llvm::APInt::getBitWidth(), llvm::SDValue::getOpcode(), and llvm::SDValue::getOperand().
| ARMTargetLowering::ConstraintType ARMTargetLowering::getConstraintType | ( | const std::string & | Constraint | ) | const [virtual] |
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 1821 of file ARMISelLowering.cpp.
References llvm::TargetLowering::C_RegisterClass, and llvm::TargetLowering::getConstraintType().
| std::pair< unsigned, const TargetRegisterClass * > ARMTargetLowering::getRegForInlineAsmConstraint | ( | const std::string & | Constraint, | |
| MVT | VT | |||
| ) | const [virtual] |
getRegForInlineAsmConstraint - Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register.
Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.
This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer..
Reimplemented from llvm::TargetLowering.
Definition at line 1833 of file ARMISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, and llvm::TargetLowering::getRegForInlineAsmConstraint().
| std::vector< unsigned > ARMTargetLowering::getRegClassForInlineAsmConstraint | ( | const std::string & | Constraint, | |
| MVT | VT | |||
| ) | const [virtual] |
getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), return a list of registers that can be used to satisfy the constraint. This should only be used for C_RegisterClass constraints.
Reimplemented from llvm::TargetLowering.
Definition at line 1855 of file ARMISelLowering.cpp.
References llvm::X86II::D8, llvm::X86II::D9, llvm::MVT::f32, and llvm::MVT::f64.
| virtual const ARMSubtarget* llvm::ARMTargetLowering::getSubtarget | ( | ) | [inline, virtual] |
Generated on Thu Nov 5 23:53:10 2009 for LLVM by
1.5.6
Copyright © 2003-2007 University of Illinois at Urbana-Champaign.
All Rights Reserved.