llvm::PPCHazardRecognizer970 Class Reference

#include <PPCHazardRecognizers.h>

Inheritance diagram for llvm::PPCHazardRecognizer970:

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Collaboration diagram for llvm::PPCHazardRecognizer970:

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List of all members.

Public Member Functions
	PPCHazardRecognizer970 (const TargetInstrInfo &TII)
virtual HazardType	getHazardType (SUnit *SU)
virtual void	EmitInstruction (SUnit *SU)
virtual void	AdvanceCycle ()

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Detailed Description

PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on the PowerPC 970 (aka G5) processor. This promotes good dispatch group formation and implements noop insertion to avoid structural hazards that cause significant performance penalties (e.g. setting the CTR register then branching through it within a dispatch group), or storing then loading from the same address within a dispatch group.

Definition at line 29 of file PPCHazardRecognizers.h.

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Constructor & Destructor Documentation

PPCHazardRecognizer970::PPCHazardRecognizer970

(

const TargetInstrInfo &

TII

)

Definition at line 48 of file PPCHazardRecognizers.cpp.

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Member Function Documentation

ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::getHazardType

(

SUnit *

SU

)

[virtual]

getHazardType - We return hazard for any non-branch instruction that would terminate terminate the dispatch group. We turn NoopHazard for any instructions that wouldn't terminate the dispatch group that would cause a pipeline flush.

Reimplemented from llvm::ScheduleHazardRecognizer.

Definition at line 123 of file PPCHazardRecognizers.cpp.

References llvm::PPCISD::BCTRL_ELF, llvm::PPCISD::BCTRL_Macho, llvm::SDNode::getFlaggedMachineNode(), llvm::SDNode::getMachineOpcode(), llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ScheduleHazardRecognizer::Hazard, Node, llvm::ScheduleHazardRecognizer::NoHazard, llvm::ScheduleHazardRecognizer::NoopHazard, llvm::PPCII::PPC970_BRU, llvm::PPCII::PPC970_CRU, llvm::PPCII::PPC970_FPU, llvm::PPCII::PPC970_FXU, llvm::PPCII::PPC970_LSU, llvm::PPCII::PPC970_Pseudo, llvm::PPCII::PPC970_VALU, and llvm::PPCII::PPC970_VPERM.

void PPCHazardRecognizer970::EmitInstruction

(

SUnit *

)

[virtual]

EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard state.

Reimplemented from llvm::ScheduleHazardRecognizer.

Definition at line 222 of file PPCHazardRecognizers.cpp.

References llvm::SDNode::getFlaggedMachineNode(), llvm::SDNode::getMachineOpcode(), llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::PPCISD::MTCTR, Node, llvm::PPCII::PPC970_BRU, llvm::PPCII::PPC970_Pseudo, llvm::PPCISD::STD_32, and llvm::PPCISD::STFIWX.

void PPCHazardRecognizer970::AdvanceCycle

(

)

[virtual]

AdvanceCycle - This callback is invoked when no instructions can be issued on this cycle without a hazard. This should increment the internal state of the hazard recognizer so that previously "Hazard" instructions will now not be hazards.

Reimplemented from llvm::ScheduleHazardRecognizer.

Definition at line 299 of file PPCHazardRecognizers.cpp.

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The documentation for this class was generated from the following files:

• PPCHazardRecognizers.h
• PPCHazardRecognizers.cpp