llvm::PPCInstrInfo Member List

This is the complete list of members for llvm::PPCInstrInfo, including all inherited members.

AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const	llvm::PPCInstrInfo	[virtual]
BlockHasNoFallThrough(const MachineBasicBlock &MBB) const	llvm::PPCInstrInfo	[virtual]
canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops) const	llvm::PPCInstrInfo	[virtual]
CommuteChangesDestination(MachineInstr *MI, unsigned &OpIdx) const	llvm::TargetInstrInfoImpl	[virtual]
commuteInstruction(MachineInstr *MI, bool NewMI) const	llvm::PPCInstrInfo	[virtual]
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const	llvm::TargetInstrInfo	[inline, virtual]
copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const	llvm::PPCInstrInfo	[virtual]
DBG_LABEL enum value	llvm::TargetInstrInfo
DECLARE enum value	llvm::TargetInstrInfo
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const	llvm::TargetInstrInfo	[inline, virtual]
EH_LABEL enum value	llvm::TargetInstrInfo
EXTRACT_SUBREG enum value	llvm::TargetInstrInfo
foldMemoryOperand(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const	llvm::TargetInstrInfo
foldMemoryOperand(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const	llvm::TargetInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const	llvm::PPCInstrInfo	[virtual]
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const	llvm::PPCInstrInfo	[inline, virtual]
GC_LABEL enum value	llvm::TargetInstrInfo
get(unsigned Opcode) const	llvm::TargetInstrInfo	[inline]
GetFunctionSizeInBytes(const MachineFunction &MF) const	llvm::TargetInstrInfoImpl	[virtual]
GetInstSizeInBytes(const MachineInstr *MI) const	llvm::PPCInstrInfo	[virtual]
getNumOpcodes() const	llvm::TargetInstrInfo	[inline]
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore) const	llvm::TargetInstrInfo	[inline, virtual]
getPointerRegClass() const	llvm::PPCInstrInfo	[virtual]
getRegisterInfo() const	llvm::PPCInstrInfo	[inline, virtual]
IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const	llvm::TargetInstrInfo	[inline, virtual]
IMPLICIT_DEF enum value	llvm::TargetInstrInfo
INLINEASM enum value	llvm::TargetInstrInfo
INSERT_SUBREG enum value	llvm::TargetInstrInfo
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond) const	llvm::PPCInstrInfo	[virtual]
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const	llvm::PPCInstrInfo	[virtual]
isInvariantLoad(const MachineInstr *MI) const	llvm::TargetInstrInfo	[inline, virtual]
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::PPCInstrInfo	[virtual]
isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SrcSubIdx, unsigned &DstSubIdx) const	llvm::PPCInstrInfo	[virtual]
isPredicated(const MachineInstr *MI) const	llvm::TargetInstrInfo	[inline, virtual]
isReallyTriviallyReMaterializable(const MachineInstr *MI) const	llvm::TargetInstrInfo	[inline, protected, virtual]
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::PPCInstrInfo	[virtual]
isTriviallyReMaterializable(const MachineInstr *MI) const	llvm::TargetInstrInfo	[inline]
isUnpredicatedTerminator(const MachineInstr *MI) const	llvm::TargetInstrInfo	[virtual]
loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::PPCInstrInfo	[virtual]
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC) const	llvm::PPCInstrInfo	[virtual]
PHI enum value	llvm::TargetInstrInfo
PPCInstrInfo(PPCTargetMachine &TM)	llvm::PPCInstrInfo	[explicit]
PredicateInstruction(MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const	llvm::TargetInstrInfoImpl	[virtual]
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const	llvm::TargetInstrInfoImpl	[virtual]
RemoveBranch(MachineBasicBlock &MBB) const	llvm::PPCInstrInfo	[virtual]
restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI) const	llvm::TargetInstrInfo	[inline, virtual]
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const	llvm::PPCInstrInfo	[virtual]
spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI) const	llvm::TargetInstrInfo	[inline, virtual]
storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::PPCInstrInfo	[virtual]
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC) const	llvm::PPCInstrInfo	[virtual]
SUBREG_TO_REG enum value	llvm::TargetInstrInfo
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const	llvm::TargetInstrInfo	[inline, virtual]
TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes)	llvm::TargetInstrInfo
TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)	llvm::TargetInstrInfoImpl	[inline, protected]
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::TargetInstrInfo	[inline, virtual]
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const	llvm::TargetInstrInfo	[inline, virtual]
~TargetInstrInfo()	llvm::TargetInstrInfo	[virtual]