llvm::PPCTargetLowering Class Reference

#include <PPCISelLowering.h>

Inheritance diagram for llvm::PPCTargetLowering:

[legend]

Collaboration diagram for llvm::PPCTargetLowering:

[legend]

List of all members.

Public Member Functions
	PPCTargetLowering (PPCTargetMachine &TM)
virtual const char *	getTargetNodeName (unsigned Opcode) const
virtual MVT	getSetCCResultType (MVT VT) const
	getSetCCResultType - Return the ISD::SETCC ValueType
virtual bool	getPreIndexedAddressParts (SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const
bool	SelectAddressRegReg (SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
bool	SelectAddressRegImm (SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
bool	SelectAddressRegRegOnly (SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
bool	SelectAddressRegImmShift (SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
virtual SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG)
virtual void	ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
virtual SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const
virtual void	computeMaskedBitsForTargetNode (const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
virtual MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB)
MachineBasicBlock *	EmitAtomicBinary (MachineInstr *MI, MachineBasicBlock *MBB, bool is64Bit, unsigned BinOpcode)
MachineBasicBlock *	EmitPartwordAtomicBinary (MachineInstr *MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode)
ConstraintType	getConstraintType (const std::string &Constraint) const
std::pair< unsigned, const TargetRegisterClass * >	getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const
unsigned	getByValTypeAlignment (const Type *Ty) const
virtual void	LowerAsmOperandForConstraint (SDValue Op, char ConstraintLetter, bool hasMemory, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
virtual bool	isLegalAddressingMode (const AddrMode &AM, const Type *Ty) const
virtual bool	isLegalAddressImmediate (int64_t V, const Type *Ty) const
virtual bool	isLegalAddressImmediate (GlobalValue *GV) const
virtual bool	IsEligibleForTailCallOptimization (CallSDNode *TheCall, SDValue Ret, SelectionDAG &DAG) const
virtual bool	isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const

---

Detailed Description

Definition at line 216 of file PPCISelLowering.h.

---

Constructor & Destructor Documentation

PPCTargetLowering::PPCTargetLowering

(

PPCTargetMachine &

TM

)

[explicit]

Definition at line 41 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::AddPromotedToType(), llvm::TargetLowering::addRegisterClass(), llvm::ISD::AND, llvm::ISD::BIT_CONVERT, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::computeRegisterProperties(), llvm::ISD::ConstantPool, llvm::RTLIB::COS_PPCF128, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::TargetLowering::Custom, llvm::ISD::DBG_STOPPOINT, llvm::ISD::DEBUG_LOC, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EHSELECTION, llvm::ISD::EXCEPTIONADDR, llvm::RTLIB::EXP2_PPCF128, llvm::RTLIB::EXP_PPCF128, llvm::TargetLowering::Expand, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FNEG, llvm::ISD::FP_ROUND_INREG, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FPOW, llvm::ISD::FREM, llvm::ISD::FSIN, llvm::ISD::FSQRT, llvm::TargetMachine::getSubtarget(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, llvm::MVT::LAST_VECTOR_VALUETYPE, llvm::TargetLowering::Legal, llvm::ISD::LOAD, llvm::RTLIB::LOG10_PPCF128, llvm::RTLIB::LOG2_PPCF128, llvm::RTLIB::LOG_PPCF128, llvm::ISD::MUL, llvm::ISD::OR, llvm::MVT::Other, llvm::RTLIB::POW_PPCF128, llvm::MVT::ppcf128, llvm::ISD::PRE_INC, llvm::TargetLowering::Promote, llvm::RTLIB::REM_PPCF128, llvm::ISD::RET, llvm::ISD::ROTR, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::TargetLowering::setBooleanContents(), llvm::ISD::SETCC, llvm::TargetLowering::setCondCodeAction(), llvm::TargetLowering::setConvertAction(), llvm::TargetLowering::setExceptionPointerRegister(), llvm::TargetLowering::setExceptionSelectorRegister(), llvm::TargetLowering::setIndexedLoadAction(), llvm::TargetLowering::setIndexedStoreAction(), llvm::TargetLowering::setLibcallName(), llvm::TargetLowering::setLoadExtAction(), llvm::ISD::SETOGE, llvm::ISD::SETOLE, llvm::ISD::SETONE, llvm::TargetLowering::setOperationAction(), llvm::TargetLowering::setPow2DivIsCheap(), llvm::TargetLowering::setShiftAmountType(), llvm::TargetLowering::setStackPointerRegisterToSaveRestore(), llvm::TargetLowering::setTargetDAGCombine(), llvm::TargetLowering::setTruncStoreAction(), llvm::ISD::SETUEQ, llvm::ISD::SETUGT, llvm::ISD::SETULT, llvm::TargetLowering::setUseUnderscoreLongJmp(), llvm::TargetLowering::setUseUnderscoreSetJmp(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND_INREG, llvm::RTLIB::SIN_PPCF128, llvm::ISD::SINT_TO_FP, llvm::ISD::SMUL_LOHI, llvm::RTLIB::SQRT_PPCF128, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::ISD::SRL_PARTS, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRAMPOLINE, llvm::ISD::TRAP, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UMUL_LOHI, llvm::ISD::UREM, llvm::MVT::v16i8, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, VT, llvm::ISD::XOR, and llvm::TargetLowering::ZeroOrOneBooleanContent.

---

Member Function Documentation

const char * PPCTargetLowering::getTargetNodeName

(

unsigned

Opcode

)

const [virtual]

getTargetNodeName() - This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 390 of file PPCISelLowering.cpp.

References llvm::PPCISD::BCTRL_ELF, llvm::PPCISD::BCTRL_Macho, llvm::PPCISD::CALL_ELF, llvm::PPCISD::CALL_Macho, llvm::PPCISD::COND_BRANCH, llvm::PPCISD::DYNALLOC, llvm::PPCISD::EXTSW_32, llvm::PPCISD::FADDRTZ, llvm::PPCISD::FCFID, llvm::PPCISD::FCTIDZ, llvm::PPCISD::FCTIWZ, llvm::PPCISD::FSEL, llvm::PPCISD::GlobalBaseReg, llvm::PPCISD::Hi, llvm::PPCISD::LARX, llvm::PPCISD::LBRX, llvm::PPCISD::Lo, llvm::PPCISD::MFCR, llvm::PPCISD::MFFS, llvm::PPCISD::MTCTR, llvm::PPCISD::MTFSB0, llvm::PPCISD::MTFSB1, llvm::PPCISD::MTFSF, llvm::PPCISD::RET_FLAG, llvm::PPCISD::SHL, llvm::PPCISD::SRA, llvm::PPCISD::SRL, llvm::PPCISD::STBRX, llvm::PPCISD::STCX, llvm::PPCISD::STD_32, llvm::PPCISD::STFIWX, llvm::PPCISD::TAILCALL, llvm::PPCISD::TC_RETURN, llvm::PPCISD::VCMP, llvm::PPCISD::VCMPo, llvm::PPCISD::VMADDFP, llvm::PPCISD::VNMSUBFP, and llvm::PPCISD::VPERM.

MVT PPCTargetLowering::getSetCCResultType

(

MVT

VT

)

const [virtual]

getSetCCResultType - Return the ISD::SETCC ValueType

Reimplemented from llvm::TargetLowering.

Definition at line 435 of file PPCISelLowering.cpp.

References llvm::MVT::i32.

bool PPCTargetLowering::getPreIndexedAddressParts	(	SDNode *	N,
		SDValue &	Base,
		SDValue &	Offset,
		ISD::MemIndexedMode &	AM,
		SelectionDAG &	DAG
	)			const [virtual]

getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Reimplemented from llvm::TargetLowering.

Definition at line 1014 of file PPCISelLowering.cpp.

References EnablePPCPreinc, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::isVector(), llvm::ISD::PRE_INC, SelectAddressRegImm(), SelectAddressRegImmShift(), llvm::ISD::SEXTLOAD, and VT.

bool PPCTargetLowering::SelectAddressRegReg	(	SDValue	N,
		SDValue &	Base,
		SDValue &	Index,
		SelectionDAG &	DAG
	)			const

SelectAddressRegReg - Given the specified addressed, check to see if it can be represented as an indexed [r+r] operation. Returns false if it can be more efficiently represented with [r+imm].

SelectAddressRegReg - Given the specified addressed, check to see if it can be represented as an indexed [r+r] operation. Returns false if it can be more efficiently represented with [r+imm].

Definition at line 767 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::ComputeMaskedBits(), llvm::APInt::getAllOnesValue(), llvm::APInt::getBoolValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), isIntS16Immediate(), llvm::PPCISD::Lo, and llvm::ISD::OR.

Referenced by SelectAddressRegImm(), SelectAddressRegImmShift(), and SelectAddressRegRegOnly().

bool PPCTargetLowering::SelectAddressRegImm	(	SDValue	N,
		SDValue &	Disp,
		SDValue &	Base,
		SelectionDAG &	DAG
	)			const

SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a signed 16-bit displacement [r+imm], and if it is not better represented as reg+reg.

Returns true if the address N can be represented by a base register plus a signed 16-bit displacement [r+imm], and if it is not better represented as reg+reg.

Definition at line 815 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::ComputeMaskedBits(), FI, llvm::APInt::getAllOnesValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLowering::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::getTargetNode(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::MVT::i32, Imm, isIntS16Immediate(), llvm::PPCISD::Lo, llvm::ISD::OR, SelectAddressRegReg(), llvm::ISD::TargetConstantPool, llvm::ISD::TargetGlobalAddress, and llvm::ISD::TargetJumpTable.

Referenced by getPreIndexedAddressParts().

bool PPCTargetLowering::SelectAddressRegRegOnly	(	SDValue	N,
		SDValue &	Base,
		SDValue &	Index,
		SelectionDAG &	DAG
	)			const

SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+r] operation.

SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+r] operation.

Definition at line 900 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getValueType(), and SelectAddressRegReg().

bool PPCTargetLowering::SelectAddressRegImmShift	(	SDValue	N,
		SDValue &	Disp,
		SDValue &	Base,
		SelectionDAG &	DAG
	)			const

SelectAddressRegImmShift - Returns true if the address N can be represented by a base register plus a signed 14-bit displacement [r+imm*4]. Suitable for use by STD and friends.

SelectAddressRegImmShift - Returns true if the address N can be represented by a base register plus a signed 14-bit displacement [r+imm*4]. Suitable for use by STD and friends.

Definition at line 927 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::ComputeMaskedBits(), FI, llvm::APInt::getAllOnesValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLowering::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::getTargetNode(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::MVT::i32, Imm, isIntS16Immediate(), llvm::PPCISD::Lo, llvm::ISD::OR, SelectAddressRegReg(), llvm::ISD::TargetConstantPool, llvm::ISD::TargetGlobalAddress, and llvm::ISD::TargetJumpTable.

Referenced by getPreIndexedAddressParts().

SDValue PPCTargetLowering::LowerOperation	(	SDValue	Op,
		SelectionDAG &	DAG
	)			[virtual]

LowerOperation - Provide custom lowering hooks for some operations.

Reimplemented from llvm::TargetLowering.

Definition at line 3784 of file PPCISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::ISD::CALL, llvm::ISD::ConstantPool, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FORMAL_ARGUMENTS, llvm::ISD::FP_TO_SINT, llvm::ISD::FRAMEADDR, llvm::SDValue::getOpcode(), llvm::TargetLowering::getTargetMachine(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, llvm::ISD::MUL, llvm::ISD::RET, llvm::ISD::RETURNADDR, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL_PARTS, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA_PARTS, llvm::ISD::SRL_PARTS, llvm::ISD::STACKRESTORE, llvm::ISD::TRAMPOLINE, llvm::ISD::VAARG, llvm::ISD::VASTART, and llvm::ISD::VECTOR_SHUFFLE.

void PPCTargetLowering::ReplaceNodeResults	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)			[virtual]

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.

Reimplemented from llvm::TargetLowering.

Definition at line 3837 of file PPCISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, llvm::ISD::EXTRACT_ELEMENT, llvm::MVT::f64, llvm::PPCISD::FADDRTZ, llvm::MVT::Flag, llvm::ISD::FP_ROUND_INREG, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::PPCISD::MFFS, llvm::PPCISD::MTFSB0, llvm::PPCISD::MTFSB1, llvm::PPCISD::MTFSF, llvm::MVT::ppcf128, and llvm::SmallVectorImpl< T >::push_back().

SDValue PPCTargetLowering::PerformDAGCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)			const [virtual]

PerformDAGCombine - This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented from llvm::TargetLowering.

Definition at line 4434 of file PPCISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::ANY_EXTEND, llvm::ISD::BR, llvm::ISD::BR_CC, llvm::ISD::BSWAP, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::PPCISD::COND_BRANCH, llvm::TargetLowering::DAGCombinerInfo::DAG, E, llvm::MVT::f32, llvm::MVT::f64, llvm::PPCISD::FCFID, llvm::PPCISD::FCTIDZ, llvm::PPCISD::FCTIWZ, llvm::MVT::Flag, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, getAltivecCompareInfo(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getRegister(), llvm::TargetMachine::getSubtarget(), llvm::TargetLowering::getTargetMachine(), llvm::SDValue::getValue(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::SDNode::hasNUsesOfValue(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MVT::i16, llvm::MVT::i64, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::isNON_EXTLoad(), llvm::PPCISD::LBRX, llvm::PPCISD::MFCR, llvm::MVT::Other, llvm::MVT::ppcf128, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::PPCISD::SHL, llvm::ISD::SINT_TO_FP, llvm::PPCISD::SRA, llvm::PPCISD::SRL, llvm::PPCISD::STBRX, llvm::PPCISD::STFIWX, llvm::ISD::STORE, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::PPCISD::VCMP, and llvm::PPCISD::VCMPo.

void PPCTargetLowering::computeMaskedBitsForTargetNode	(	const SDValue	Op,
		const APInt &	Mask,
		APInt &	KnownZero,
		APInt &	KnownOne,
		const SelectionDAG &	DAG,
		unsigned	Depth = 0
	)			const [virtual]

computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Reimplemented from llvm::TargetLowering.

Definition at line 4689 of file PPCISelLowering.cpp.

References llvm::APInt::getBitWidth(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::i16, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::PPCISD::LBRX, llvm::Intrinsic::ppc_altivec_vcmpbfp_p, llvm::Intrinsic::ppc_altivec_vcmpeqfp_p, llvm::Intrinsic::ppc_altivec_vcmpequb_p, llvm::Intrinsic::ppc_altivec_vcmpequh_p, llvm::Intrinsic::ppc_altivec_vcmpequw_p, llvm::Intrinsic::ppc_altivec_vcmpgefp_p, llvm::Intrinsic::ppc_altivec_vcmpgtfp_p, llvm::Intrinsic::ppc_altivec_vcmpgtsb_p, llvm::Intrinsic::ppc_altivec_vcmpgtsh_p, llvm::Intrinsic::ppc_altivec_vcmpgtsw_p, llvm::Intrinsic::ppc_altivec_vcmpgtub_p, llvm::Intrinsic::ppc_altivec_vcmpgtuh_p, and llvm::Intrinsic::ppc_altivec_vcmpgtuw_p.

MachineBasicBlock * PPCTargetLowering::EmitInstrWithCustomInserter	(	MachineInstr *	MI,
		MachineBasicBlock *	MBB
	)			[virtual]

Reimplemented from llvm::TargetLowering.

Definition at line 4097 of file PPCISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::ISD::AND, llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineFunction::DeleteMachineInstr(), EmitAtomicBinary(), EmitPartwordAtomicBinary(), F, llvm::TargetInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineOperand::getImm(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetLowering::getTargetMachine(), llvm::MachineFunction::insert(), llvm::PPCSubtarget::isPPC64(), LI, llvm::ISD::OR, PHI, llvm::PPC::PRED_NE, TII, llvm::MachineBasicBlock::transferSuccessors(), and llvm::ISD::XOR.

MachineBasicBlock * PPCTargetLowering::EmitAtomicBinary	(	MachineInstr *	MI,
		MachineBasicBlock *	MBB,
		bool	is64Bit,
		unsigned	BinOpcode
	)

Definition at line 3914 of file PPCISelLowering.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), F, llvm::TargetInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetLowering::getTargetMachine(), llvm::MachineFunction::insert(), llvm::PPC::PRED_NE, TII, and llvm::MachineBasicBlock::transferSuccessors().

Referenced by EmitInstrWithCustomInserter().

MachineBasicBlock * PPCTargetLowering::EmitPartwordAtomicBinary	(	MachineInstr *	MI,
		MachineBasicBlock *	MBB,
		bool	is8bit,
		unsigned	Opcode
	)

Definition at line 3971 of file PPCISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::ISD::AND, llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), F, llvm::TargetInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetLowering::getTargetMachine(), llvm::MachineFunction::insert(), llvm::PPCSubtarget::isPPC64(), LI, llvm::ISD::OR, llvm::PPC::PRED_NE, TII, and llvm::MachineBasicBlock::transferSuccessors().

Referenced by EmitInstrWithCustomInserter().

PPCTargetLowering::ConstraintType PPCTargetLowering::getConstraintType

(

const std::string &

Constraint

)

const [virtual]

getConstraintType - Given a constraint, return the type of constraint it is for this target.

Reimplemented from llvm::TargetLowering.

Definition at line 4731 of file PPCISelLowering.cpp.

References llvm::TargetLowering::C_RegisterClass, and llvm::TargetLowering::getConstraintType().

std::pair< unsigned, const TargetRegisterClass * > PPCTargetLowering::getRegForInlineAsmConstraint	(	const std::string &	Constraint,
		MVT	VT
	)			const [virtual]

getRegForInlineAsmConstraint - Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register.

Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.

This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer..

Reimplemented from llvm::TargetLowering.

Definition at line 4747 of file PPCISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MVT::i64, and llvm::PPCSubtarget::isPPC64().

unsigned PPCTargetLowering::getByValTypeAlignment

(

const Type *

Ty

)

const [virtual]

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. This is the actual alignment, not its logarithm.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.

Reimplemented from llvm::TargetLowering.

Definition at line 381 of file PPCISelLowering.cpp.

References llvm::TargetMachine::getSubtarget(), llvm::TargetLowering::getTargetMachine(), and TM.

void PPCTargetLowering::LowerAsmOperandForConstraint	(	SDValue	Op,
		char	Letter,
		bool	hasMemory,
		std::vector< SDValue > &	Ops,
		SelectionDAG &	DAG
	)			const [virtual]

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.

Reimplemented from llvm::TargetLowering.

Definition at line 4778 of file PPCISelLowering.cpp.

References llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::isPowerOf2_32(), and llvm::TargetLowering::LowerAsmOperandForConstraint().

bool PPCTargetLowering::isLegalAddressingMode	(	const AddrMode &	AM,
		const Type *	Ty
	)			const [virtual]

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLowering.

Definition at line 4843 of file PPCISelLowering.cpp.

References llvm::TargetLowering::AddrMode::BaseGV, llvm::TargetLowering::AddrMode::BaseOffs, llvm::TargetLowering::AddrMode::HasBaseReg, and llvm::TargetLowering::AddrMode::Scale.

bool PPCTargetLowering::isLegalAddressImmediate	(	int64_t	V,
		const Type *	Ty
	)			const [virtual]

isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.

isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.

Definition at line 4880 of file PPCISelLowering.cpp.

bool PPCTargetLowering::isLegalAddressImmediate

(

llvm::GlobalValue *

GV

)

const [virtual]

isLegalAddressImmediate - Return true if the GlobalValue can be used as the offset of the target addressing mode.

Definition at line 4885 of file PPCISelLowering.cpp.

bool PPCTargetLowering::IsEligibleForTailCallOptimization	(	CallSDNode *	TheCall,
		SDValue	Ret,
		SelectionDAG &	DAG
	)			const [virtual]

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization. Target which want to do tail call optimization should implement this function.

IsEligibleForTailCallElimination - Check to see whether the next instruction following the call is a return. A function is eligible if caller/callee calling conventions match, currently only fastcc supports tail calls, and the function CALL is immediatly followed by a RET.

Reimplemented from llvm::TargetLowering.

Definition at line 1921 of file PPCISelLowering.cpp.

References llvm::TargetLowering::CheckTailCallReturnConstraints(), llvm::CallingConv::Fast, G, llvm::CallSDNode::getArgFlags(), llvm::CallSDNode::getCallee(), llvm::CallSDNode::getCallingConv(), llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::CallSDNode::getNumArgs(), llvm::TargetLowering::getTargetMachine(), llvm::ISD::ArgFlagsTy::isByVal(), llvm::CallSDNode::isVarArg(), llvm::PerformTailCallOpt, and llvm::Reloc::PIC_.

bool PPCTargetLowering::isOffsetFoldingLegal

(

const GlobalAddressSDNode *

GA

)

const [virtual]

isOffsetFoldingLegal - Return true if folding a constant offset with the given GlobalAddress is legal. It is frequently not legal in PIC relocation models.

Reimplemented from llvm::TargetLowering.

Definition at line 4928 of file PPCISelLowering.cpp.

---

The documentation for this class was generated from the following files:

• PPCISelLowering.h
• PPCISelLowering.cpp