LLVM API Documentation

llvm::SelectionDAGLowering Class Reference

#include <SelectionDAGBuild.h>

Collaboration diagram for llvm::SelectionDAGLowering:
[legend]

List of all members.

Public Member Functions

 SelectionDAGLowering (SelectionDAG &dag, TargetLowering &tli, FunctionLoweringInfo &funcinfo)
void init (GCFunctionInfo *gfi, AliasAnalysis &aa)
void clear ()
SDValue getRoot ()
SDValue getControlRoot ()
DebugLoc getCurDebugLoc () const
void CopyValueToVirtualRegister (Value *V, unsigned Reg)
void visit (Instruction &I)
void visit (unsigned Opcode, User &I)
void setCurrentBasicBlock (MachineBasicBlock *MBB)
SDValue getValue (const Value *V)
void setValue (const Value *V, SDValue NewN)
void GetRegistersForValue (SDISelAsmOperandInfo &OpInfo, std::set< unsigned > &OutputRegs, std::set< unsigned > &InputRegs)
void FindMergedConditions (Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, unsigned Opc)
 FindMergedConditions - If Cond is an expression like.
void EmitBranchForMergedCondition (Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB)
bool ShouldEmitAsBranches (const std::vector< CaseBlock > &Cases)
bool isExportableFromCurrentBlock (Value *V, const BasicBlock *FromBB)
void ExportFromCurrentBlock (Value *V)
void LowerCallTo (CallSite CS, SDValue Callee, bool IsTailCall, MachineBasicBlock *LandingPad=NULL)
void visitSwitchCase (CaseBlock &CB)
void visitBitTestHeader (BitTestBlock &B)
void visitBitTestCase (MachineBasicBlock *NextMBB, unsigned Reg, BitTestCase &B)
 visitBitTestCase - this function produces one "bit test"
void visitJumpTable (JumpTable &JT)
 visitJumpTable - Emit JumpTable node in the current MBB
void visitJumpTableHeader (JumpTable &JT, JumpTableHeader &JTH)

Public Attributes

TargetLowering & TLI
SelectionDAG & DAG
const TargetData * TD
AliasAnalysis * AA
std::vector< CaseBlock > SwitchCases
std::vector< JumpTableBlock > JTCases
std::vector< BitTestBlock > BitTestCases
std::vector< std::pair
< MachineInstr *, unsigned > > 
PHINodesToUpdate
DenseMap< Constant *, unsigned > ConstantsOut
FunctionLoweringInfo & FuncInfo
GCFunctionInfo * GFI
 GFI - Garbage collection metadata for the function.

Classes

struct  BitTestBlock
struct  BitTestCase
struct  Case
struct  CaseBits
struct  CaseBitsCmp
struct  CaseBlock
struct  CaseCmp
struct  CaseRec
struct  JumpTable
struct  JumpTableHeader


Detailed Description

SelectionDAGLowering - This is the common target-independent lowering implementation that is parameterized by a TargetLowering object. Also, targets can overload any lowering method.

Definition at line 165 of file SelectionDAGBuild.h.


Constructor & Destructor Documentation

llvm::SelectionDAGLowering::SelectionDAGLowering ( SelectionDAG &  dag,
TargetLowering &  tli,
FunctionLoweringInfo &  funcinfo 
) [inline]

Definition at line 361 of file SelectionDAGBuild.h.


Member Function Documentation

void SelectionDAGLowering::init ( GCFunctionInfo *  gfi,
AliasAnalysis &  aa 
)

void SelectionDAGLowering::clear (  ) 

clear - Clear out the curret SelectionDAG and the associated state and prepare this SelectionDAGLowering object to be used for a new block. This doesn't clear out information about additional blocks that are needed to complete switch lowering or PHI node updating; that information is cleared out as it is consumed.

clear - Clear out the curret SelectionDAG and the associated state and prepare this SelectionDAGLowering object to be used for a new block. This doesn't clear out information about additional blocks that are needed to complete switch lowering or PHI node updating; that information is cleared out as it is consumed.

Definition at line 754 of file SelectionDAGBuild.cpp.

References llvm::SelectionDAG::clear(), and DAG.

SDValue SelectionDAGLowering::getRoot (  ) 

getRoot - Return the current virtual root of the Selection DAG, flushing any PendingLoad items. This must be done before emitting a store or any other node that may need to be ordered after any prior load instructions.

getRoot - Return the current virtual root of the Selection DAG, flushing any PendingLoad items. This must be done before emitting a store or any other node that may need to be ordered after any prior load instructions.

Definition at line 766 of file SelectionDAGBuild.cpp.

References DAG, getCurDebugLoc(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRoot(), llvm::MVT::Other, Root, llvm::SelectionDAG::setRoot(), and llvm::ISD::TokenFactor.

Referenced by LowerCallTo().

SDValue SelectionDAGLowering::getControlRoot (  ) 

getControlRoot - Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports items. It is necessary to do this before emitting a terminator instruction.

getControlRoot - Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports items. It is necessary to do this before emitting a terminator instruction.

Definition at line 789 of file SelectionDAGBuild.cpp.

References DAG, llvm::ISD::EntryToken, getCurDebugLoc(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getRoot(), llvm::MVT::Other, Root, llvm::SelectionDAG::setRoot(), and llvm::ISD::TokenFactor.

Referenced by LowerCallTo(), visitBitTestCase(), visitBitTestHeader(), visitJumpTable(), visitJumpTableHeader(), and visitSwitchCase().

DebugLoc llvm::SelectionDAGLowering::getCurDebugLoc (  )  const [inline]

void SelectionDAGLowering::CopyValueToVirtualRegister ( Value *  V,
unsigned  Reg 
)

void SelectionDAGLowering::visit ( Instruction &  I  ) 

Definition at line 816 of file SelectionDAGBuild.cpp.

References llvm::Instruction::getOpcode().

Referenced by getValue().

void SelectionDAGLowering::visit ( unsigned  Opcode,
User &  I 
)

Definition at line 820 of file SelectionDAGBuild.cpp.

void llvm::SelectionDAGLowering::setCurrentBasicBlock ( MachineBasicBlock *  MBB  )  [inline]

Definition at line 398 of file SelectionDAGBuild.h.

SDValue SelectionDAGLowering::getValue ( const Value *  V  ) 

void llvm::SelectionDAGLowering::setValue ( const Value *  V,
SDValue  NewN 
) [inline]

Definition at line 402 of file SelectionDAGBuild.h.

References llvm::SDValue::getNode().

Referenced by LowerCallTo().

void SelectionDAGLowering::GetRegistersForValue ( SDISelAsmOperandInfo &  OpInfo,
std::set< unsigned > &  OutputRegs,
std::set< unsigned > &  InputRegs 
)

GetRegistersForValue - Assign registers (virtual or physical) for the specified operand. We prefer to assign virtual registers, to allow the register allocator handle the assignment process. However, if the asm uses features that we can't model on machineinstrs, we have SDISel do the allocation. This produces generally horrible, but correct, code.

OpInfo describes the operand. Input and OutputRegs are the set of already allocated physical registers.

Definition at line 4788 of file SelectionDAGBuild.cpp.

References llvm::SDISelAsmOperandInfo::AssignedRegs, llvm::ISD::BIT_CONVERT, llvm::SDISelAsmOperandInfo::CallOperand, llvm::TargetLowering::AsmOperandInfo::ConstraintCode, llvm::TargetLowering::AsmOperandInfo::ConstraintVT, llvm::MachineRegisterInfo::createVirtualRegister(), DAG, getCurDebugLoc(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::getNumRegisters(), llvm::TargetLowering::getRegClassForInlineAsmConstraint(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MachineFunction::getRegInfo(), llvm::TargetMachine::getRegisterInfo(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTarget(), llvm::InlineAsm::ConstraintInfo::hasMatchingInput(), isAllocatableRegister(), llvm::InlineAsm::isClobber, llvm::MVT::isFloatingPoint(), llvm::InlineAsm::isInput, llvm::MVT::isInteger(), llvm::InlineAsm::isOutput, llvm::SDISelAsmOperandInfo::MarkAllocatedRegs(), llvm::MVT::Other, llvm::SmallVectorImpl< T >::push_back(), RegInfo, TLI, llvm::InlineAsm::ConstraintInfo::Type, and llvm::TargetRegisterClass::vt_begin().

void SelectionDAGLowering::FindMergedConditions ( Value *  Cond,
MachineBasicBlock *  TBB,
MachineBasicBlock *  FBB,
MachineBasicBlock *  CurBB,
unsigned  Opc 
)

void SelectionDAGLowering::EmitBranchForMergedCondition ( Value *  Cond,
MachineBasicBlock *  TBB,
MachineBasicBlock *  FBB,
MachineBasicBlock *  CurBB 
)

EmitBranchForMergedCondition - Helper method for FindMergedConditions. This function emits a branch and is used at the leaves of an OR or an AND operator tree.

Definition at line 1121 of file SelectionDAGBuild.cpp.

References BB, llvm::MachineBasicBlock::getBasicBlock(), getFCmpCondCode(), getICmpCondCode(), llvm::ConstantInt::getTrue(), IC, isExportableFromCurrentBlock(), llvm::ISD::SETEQ, and SwitchCases.

Referenced by FindMergedConditions().

bool SelectionDAGLowering::ShouldEmitAsBranches ( const std::vector< CaseBlock > &  Cases  ) 

If the set of cases should be emitted as a series of branches, return true. If we should emit this as a bunch of and/or'd together conditions, return false.

Definition at line 1219 of file SelectionDAGBuild.cpp.

bool SelectionDAGLowering::isExportableFromCurrentBlock ( Value *  V,
const BasicBlock *  FromBB 
)

void SelectionDAGLowering::ExportFromCurrentBlock ( Value *  V  ) 

ExportFromCurrentBlock - If this condition isn't known to be exported from the current basic block, add it to ValueMap now so that we'll get a CopyTo/FromReg.

Definition at line 1017 of file SelectionDAGBuild.cpp.

References CopyValueToVirtualRegister(), FuncInfo, llvm::FunctionLoweringInfo::InitializeRegForValue(), llvm::FunctionLoweringInfo::isExportedInst(), and Reg.

void SelectionDAGLowering::LowerCallTo ( CallSite  CS,
SDValue  Callee,
bool  IsTailCall,
MachineBasicBlock *  LandingPad = NULL 
)

void SelectionDAGLowering::visitSwitchCase ( CaseBlock &  CB  ) 

void SelectionDAGLowering::visitBitTestHeader ( BitTestBlock &  B  ) 

void SelectionDAGLowering::visitBitTestCase ( MachineBasicBlock *  NextMBB,
unsigned  Reg,
BitTestCase &  B 
)

void SelectionDAGLowering::visitJumpTable ( JumpTable &  JT  ) 

void SelectionDAGLowering::visitJumpTableHeader ( JumpTable &  JT,
JumpTableHeader &  JTH 
)


Member Data Documentation

Definition at line 335 of file SelectionDAGBuild.h.

Referenced by init().

Definition at line 336 of file SelectionDAGBuild.h.

Referenced by init().

SwitchCases - Vector of CaseBlock structures used to communicate SwitchInst code generation information.

Definition at line 340 of file SelectionDAGBuild.h.

Referenced by EmitBranchForMergedCondition().

std::vector<JumpTableBlock> llvm::SelectionDAGLowering::JTCases

JTCases - Vector of JumpTable structures used to communicate SwitchInst code generation information.

Definition at line 343 of file SelectionDAGBuild.h.

std::vector<BitTestBlock> llvm::SelectionDAGLowering::BitTestCases

BitTestCases - Vector of BitTestBlock structures used to communicate SwitchInst code generation information.

Definition at line 346 of file SelectionDAGBuild.h.

Definition at line 348 of file SelectionDAGBuild.h.

Definition at line 352 of file SelectionDAGBuild.h.

FuncInfo - Information about the function as a whole.

Definition at line 356 of file SelectionDAGBuild.h.

Referenced by ExportFromCurrentBlock(), getValue(), isExportableFromCurrentBlock(), visitBitTestHeader(), and visitJumpTableHeader().

GFI - Garbage collection metadata for the function.

Definition at line 359 of file SelectionDAGBuild.h.

Referenced by init().


The documentation for this class was generated from the following files: