LLVM API Documentation

llvm::SparcInstrInfo Member List

This is the complete list of members for llvm::SparcInstrInfo, including all inherited members.

AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const llvm::TargetInstrInfo [inline, virtual]
BlockHasNoFallThrough(const MachineBasicBlock &MBB) const llvm::TargetInstrInfo [inline, virtual]
canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops) const llvm::TargetInstrInfo [inline, virtual]
CommuteChangesDestination(MachineInstr *MI, unsigned &OpIdx) const llvm::TargetInstrInfoImpl [virtual]
commuteInstruction(MachineInstr *MI, bool NewMI=false) const llvm::TargetInstrInfoImpl [virtual]
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const llvm::TargetInstrInfo [inline, virtual]
copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const llvm::SparcInstrInfo [virtual]
DBG_LABEL enum valuellvm::TargetInstrInfo
DECLARE enum valuellvm::TargetInstrInfo
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const llvm::TargetInstrInfo [inline, virtual]
EH_LABEL enum valuellvm::TargetInstrInfo
EXTRACT_SUBREG enum valuellvm::TargetInstrInfo
foldMemoryOperand(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const llvm::TargetInstrInfo
foldMemoryOperand(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const llvm::TargetInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const llvm::SparcInstrInfo [virtual]
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const llvm::SparcInstrInfo [inline, virtual]
GC_LABEL enum valuellvm::TargetInstrInfo
get(unsigned Opcode) const llvm::TargetInstrInfo [inline]
GetFunctionSizeInBytes(const MachineFunction &MF) const llvm::TargetInstrInfoImpl [virtual]
GetInstSizeInBytes(const MachineInstr *MI) const llvm::TargetInstrInfo [inline, virtual]
getNumOpcodes() const llvm::TargetInstrInfo [inline]
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore) const llvm::TargetInstrInfo [inline, virtual]
getPointerRegClass() const llvm::TargetInstrInfo [inline, virtual]
getRegisterInfo() const llvm::SparcInstrInfo [inline, virtual]
IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const llvm::TargetInstrInfo [inline, virtual]
IMPLICIT_DEF enum valuellvm::TargetInstrInfo
INLINEASM enum valuellvm::TargetInstrInfo
INSERT_SUBREG enum valuellvm::TargetInstrInfo
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond) const llvm::SparcInstrInfo [virtual]
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const llvm::TargetInstrInfo [inline, virtual]
isInvariantLoad(const MachineInstr *MI) const llvm::TargetInstrInfo [inline, virtual]
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const llvm::SparcInstrInfo [virtual]
isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SrcSubIdx, unsigned &DstSubIdx) const llvm::SparcInstrInfo [virtual]
isPredicated(const MachineInstr *MI) const llvm::TargetInstrInfo [inline, virtual]
isReallyTriviallyReMaterializable(const MachineInstr *MI) const llvm::TargetInstrInfo [inline, protected, virtual]
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const llvm::SparcInstrInfo [virtual]
isTriviallyReMaterializable(const MachineInstr *MI) const llvm::TargetInstrInfo [inline]
isUnpredicatedTerminator(const MachineInstr *MI) const llvm::TargetInstrInfo [virtual]
loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const llvm::SparcInstrInfo [virtual]
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC) const llvm::SparcInstrInfo [virtual]
PHI enum valuellvm::TargetInstrInfo
PredicateInstruction(MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const llvm::TargetInstrInfoImpl [virtual]
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const llvm::TargetInstrInfoImpl [virtual]
RemoveBranch(MachineBasicBlock &MBB) const llvm::TargetInstrInfo [inline, virtual]
restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI) const llvm::TargetInstrInfo [inline, virtual]
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const llvm::TargetInstrInfo [inline, virtual]
SparcInstrInfo(SparcSubtarget &ST)llvm::SparcInstrInfo [explicit]
spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI) const llvm::TargetInstrInfo [inline, virtual]
storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const llvm::SparcInstrInfo [virtual]
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC) const llvm::SparcInstrInfo [virtual]
SUBREG_TO_REG enum valuellvm::TargetInstrInfo
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const llvm::TargetInstrInfo [inline, virtual]
TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes)llvm::TargetInstrInfo
TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)llvm::TargetInstrInfoImpl [inline, protected]
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const llvm::TargetInstrInfo [inline, virtual]
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const llvm::TargetInstrInfo [inline, virtual]
~TargetInstrInfo()llvm::TargetInstrInfo [virtual]