llvm::X86TargetLowering Class Reference

#include <X86ISelLowering.h>

Inheritance diagram for llvm::X86TargetLowering:

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Collaboration diagram for llvm::X86TargetLowering:

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List of all members.

Public Member Functions
	X86TargetLowering (X86TargetMachine &TM)
SDValue	getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
unsigned	getBytesToPopOnReturn () const
unsigned	getBytesCallerReserves () const
unsigned	getStackPtrReg () const
virtual unsigned	getByValTypeAlignment (const Type *Ty) const
virtual MVT	getOptimalMemOpType (uint64_t Size, unsigned Align, bool isSrcConst, bool isSrcStr) const
virtual SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG)
virtual void	ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
virtual SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const
virtual MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB)
virtual const char *	getTargetNodeName (unsigned Opcode) const
virtual MVT	getSetCCResultType (MVT VT) const
	getSetCCResultType - Return the ISD::SETCC ValueType
virtual void	computeMaskedBitsForTargetNode (const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
virtual bool	isGAPlusOffset (SDNode *N, GlobalValue *&GA, int64_t &Offset) const
SDValue	getReturnAddressFrameIndex (SelectionDAG &DAG)
ConstraintType	getConstraintType (const std::string &Constraint) const
std::vector< unsigned >	getRegClassForInlineAsmConstraint (const std::string &Constraint, MVT VT) const
virtual const char *	LowerXConstraint (MVT ConstraintVT) const
virtual void	LowerAsmOperandForConstraint (SDValue Op, char ConstraintLetter, bool hasMemory, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
std::pair< unsigned, const TargetRegisterClass * >	getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const
virtual bool	isLegalAddressingMode (const AddrMode &AM, const Type *Ty) const
virtual bool	isTruncateFree (const Type *Ty1, const Type *Ty2) const
virtual bool	isTruncateFree (MVT VT1, MVT VT2) const
virtual bool	isShuffleMaskLegal (SDValue Mask, MVT VT) const
virtual bool	isVectorClearMaskLegal (const std::vector< SDValue > &BVOps, MVT EVT, SelectionDAG &DAG) const
virtual bool	ShouldShrinkFPConstant (MVT VT) const
virtual bool	IsEligibleForTailCallOptimization (CallSDNode *TheCall, SDValue Ret, SelectionDAG &DAG) const
virtual const X86Subtarget *	getSubtarget ()
bool	isScalarFPTypeInSSEReg (MVT VT) const
virtual MVT	getWidenVectorType (MVT VT) const
virtual FastISel *	createFastISel (MachineFunction &mf, MachineModuleInfo *mmi, DwarfWriter *dw, DenseMap< const Value *, unsigned > &, DenseMap< const BasicBlock *, MachineBasicBlock * > &, DenseMap< const AllocaInst *, int > &, SmallSet< Instruction *, 8 > &)

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Detailed Description

Definition at line 338 of file X86ISelLowering.h.

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Constructor & Destructor Documentation

X86TargetLowering::X86TargetLowering

(

X86TargetMachine &

TM

)

[explicit]

Definition at line 50 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::addLegalFPImmediate(), llvm::TargetLowering::AddPromotedToType(), llvm::TargetLowering::addRegisterClass(), llvm::TargetLowering::allowUnalignedMemoryAccesses, llvm::ISD::AND, llvm::lltok::APFloat, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::ISD::BIT_CONVERT, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::APFloat::changeSign(), llvm::TargetLowering::computeRegisterProperties(), llvm::ISD::ConstantPool, llvm::APFloat::convert(), llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::TargetLowering::Custom, llvm::ISD::DBG_LABEL, llvm::ISD::DBG_STOPPOINT, DisableMMX, llvm::ISD::DYNAMIC_STACKALLOC, llvm::N86::EAX, llvm::N86::EDX, llvm::ISD::EH_LABEL, llvm::ISD::EH_RETURN, llvm::ISD::EHSELECTION, llvm::N86::ESP, llvm::ISD::EXCEPTIONADDR, llvm::TargetLowering::Expand, llvm::ISD::ExternalSymbol, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FABS, llvm::ISD::FADD, Fast, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_ROUND_INREG, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::ISD::FRAME_TO_ARGS_OFFSET, llvm::ISD::FREM, llvm::ISD::FSIN, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::X86TargetMachine::getRegisterInfo(), llvm::TargetMachine::getSubtarget(), llvm::TargetLowering::getTargetData(), llvm::MVT::getVectorNumElements(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE3(), llvm::X86Subtarget::hasSSE41(), llvm::X86Subtarget::hasSSE42(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::X86Subtarget::is64Bit(), llvm::isPowerOf2_32(), llvm::X86Subtarget::isTargetCygMing(), llvm::X86Subtarget::isTargetDarwin(), llvm::X86Subtarget::isTargetELF(), llvm::X86Subtarget::isTargetMingw(), llvm::ISD::JumpTable, llvm::MVT::LAST_VECTOR_VALUETYPE, llvm::TargetLowering::Legal, llvm::ISD::LOAD, llvm::TargetLowering::Mask, llvm::TargetLowering::maxStoresPerMemcpy, llvm::TargetLowering::maxStoresPerMemmove, llvm::TargetLowering::maxStoresPerMemset, llvm::ISD::MEMBARRIER, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::ISD::OR, llvm::MVT::Other, llvm::ISD::PREFETCH, llvm::TargetLowering::Promote, llvm::ISD::READCYCLECOUNTER, llvm::ISD::RET, llvm::APFloat::rmNearestTiesToEven, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::TargetLowering::SchedulingForRegPressure, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::TargetLowering::setBooleanContents(), llvm::ISD::SETCC, llvm::TargetLowering::setCondCodeAction(), llvm::TargetLowering::setConvertAction(), llvm::TargetLowering::setExceptionPointerRegister(), llvm::TargetLowering::setExceptionSelectorRegister(), llvm::TargetLowering::setLoadExtAction(), llvm::ISD::SETOEQ, llvm::TargetLowering::setOperationAction(), llvm::TargetLowering::setPrefLoopAlignment(), llvm::TargetLowering::setSchedulingPreference(), llvm::TargetLowering::setShiftAmountFlavor(), llvm::TargetLowering::setShiftAmountType(), llvm::TargetLowering::setStackPointerRegisterToSaveRestore(), llvm::TargetLowering::setTargetDAGCombine(), llvm::TargetLowering::setTruncStoreAction(), llvm::ISD::SETUNE, llvm::TargetLowering::setUseUnderscoreLongJmp(), llvm::TargetLowering::setUseUnderscoreSetJmp(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRAMPOLINE, llvm::ISD::TRAP, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UMUL_LOHI, llvm::ISD::UMULO, llvm::ISD::UNDEF, llvm::UnsafeFPMath, llvm::ISD::UREM, llvm::ISD::USUBO, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSETCC, VT, llvm::APFloat::x87DoubleExtended, llvm::ISD::XOR, and llvm::TargetLowering::ZeroOrOneBooleanContent.

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Member Function Documentation

SDValue X86TargetLowering::getPICJumpTableRelocBase	(	SDValue	Table,
		SelectionDAG &	DAG
	)			const [virtual]

getPICJumpTableRelocaBase - Returns relocation base for the given PIC jumptable.

getPICJumpTableRelocaBase - Returns relocation base for the given PIC jumptable.

Reimplemented from llvm::TargetLowering.

Definition at line 900 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::TargetLowering::getPointerTy(), llvm::ISD::GLOBAL_OFFSET_TABLE, llvm::X86ISD::GlobalBaseReg, llvm::X86Subtarget::isPICStyleRIPRel(), and llvm::TargetLowering::usesGlobalOffsetTable().

unsigned llvm::X86TargetLowering::getBytesToPopOnReturn

(

)

const [inline]

Definition at line 357 of file X86ISelLowering.h.

unsigned llvm::X86TargetLowering::getBytesCallerReserves

(

)

const [inline]

Definition at line 361 of file X86ISelLowering.h.

unsigned llvm::X86TargetLowering::getStackPtrReg

(

)

const [inline]

getStackPtrReg - Return the stack pointer register we are using: either ESP or RSP.

Definition at line 365 of file X86ISelLowering.h.

unsigned X86TargetLowering::getByValTypeAlignment

(

const Type *

Ty

)

const [virtual]

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. For X86, aggregates that contains are placed at 16-byte boundaries while the rest are at 4-byte boundaries.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. For X86, aggregates that contain SSE vectors are placed at 16-byte boundaries while the rest are at 4-byte boundaries.

Reimplemented from llvm::TargetLowering.

Definition at line 861 of file X86ISelLowering.cpp.

References Align, llvm::TargetData::getABITypeAlignment(), getMaxByValAlign(), llvm::X86Subtarget::hasSSE1(), and llvm::X86Subtarget::is64Bit().

MVT X86TargetLowering::getOptimalMemOpType	(	uint64_t	Size,
		unsigned	Align,
		bool	isSrcConst,
		bool	isSrcStr
	)			const [virtual]

getOptimalMemOpType - Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. It returns MVT::iAny if SelectionDAG should be responsible for determining it.

getOptimalMemOpType - Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. It returns MVT::iAny if SelectionDAG should be responsible for determining it.

Reimplemented from llvm::TargetLowering.

Definition at line 881 of file X86ISelLowering.cpp.

References llvm::X86Subtarget::getStackAlignment(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i32, llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), llvm::MVT::v4f32, and llvm::MVT::v4i32.

SDValue X86TargetLowering::LowerOperation	(	SDValue	Op,
		SelectionDAG &	DAG
	)			[virtual]

LowerOperation - Provide custom lowering hooks for some operations.

Reimplemented from llvm::TargetLowering.

Definition at line 6489 of file X86ISelLowering.cpp.

References llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::ISD::CALL, llvm::ISD::ConstantPool, llvm::ISD::CTLZ, llvm::ISD::CTTZ, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_RETURN, llvm::ISD::ExternalSymbol, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FCOPYSIGN, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FNEG, llvm::ISD::FORMAL_ARGUMENTS, llvm::ISD::FP_TO_SINT, llvm::ISD::FRAME_TO_ARGS_OFFSET, llvm::ISD::FRAMEADDR, llvm::SDValue::getOpcode(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, llvm::ISD::MUL, llvm::ISD::READCYCLECOUNTER, llvm::ISD::RET, llvm::ISD::RETURNADDR, llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SHL_PARTS, llvm::ISD::SINT_TO_FP, llvm::ISD::SMULO, llvm::ISD::SRA_PARTS, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::TRAMPOLINE, llvm::ISD::UADDO, llvm::ISD::UINT_TO_FP, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, and llvm::ISD::VSETCC.

void X86TargetLowering::ReplaceNodeResults	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)			[virtual]

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.

ReplaceNodeResults - Replace a node with an illegal result type with a new node built out of custom code.

Reimplemented from llvm::TargetLowering.

Definition at line 6570 of file X86ISelLowering.cpp.

References llvm::X86ISD::ATOMADD64_DAG, llvm::X86ISD::ATOMAND64_DAG, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::X86ISD::ATOMNAND64_DAG, llvm::X86ISD::ATOMOR64_DAG, llvm::X86ISD::ATOMSUB64_DAG, llvm::X86ISD::ATOMSWAP64_DAG, llvm::X86ISD::ATOMXOR64_DAG, llvm::ISD::BUILD_PAIR, llvm::N86::EAX, llvm::N86::EBX, llvm::N86::EDX, llvm::ISD::EXTRACT_ELEMENT, llvm::MVT::Flag, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::X86ISD::LCMPXCHG8_DAG, llvm::MVT::Other, llvm::SmallVectorImpl< T >::push_back(), llvm::X86ISD::RDTSC_DAG, and llvm::ISD::READCYCLECOUNTER.

SDValue X86TargetLowering::PerformDAGCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)			const [virtual]

PerformDAGCombine - This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented from llvm::TargetLowering.

Definition at line 7971 of file X86ISelLowering.cpp.

References llvm::X86ISD::BT, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::X86ISD::FAND, llvm::X86ISD::FOR, llvm::X86ISD::FXOR, llvm::SDNode::getOpcode(), PerformBTCombine(), PerformBuildVectorCombine(), PerformFANDCombine(), PerformFORCombine(), PerformSELECTCombine(), PerformShiftCombine(), PerformShuffleCombine(), PerformSTORECombine(), llvm::ISD::SELECT, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::STORE, and llvm::ISD::VECTOR_SHUFFLE.

MachineBasicBlock * X86TargetLowering::EmitInstrWithCustomInserter	(	MachineInstr *	MI,
		MachineBasicBlock *	MBB
	)			[virtual]

Reimplemented from llvm::TargetLowering.

Definition at line 7195 of file X86ISelLowering.cpp.

References llvm::addFrameReference(), llvm::addFullAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::ARMCC::AL, llvm::X86AddressMode::Base, llvm::X86AddressMode::BaseType, llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineFrameInfo::CreateStackObject(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineFunction::DeleteMachineInstr(), llvm::X86AddressMode::Disp, llvm::N86::EAX, llvm::X86ISD::FNSTCW16m, llvm::X86AddressMode::FrameIndex, llvm::X86AddressMode::FrameIndexBase, llvm::TargetInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), GetCondBranchFromCond(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetLowering::getTargetMachine(), llvm::X86AddressMode::GV, llvm::X86AddressMode::IndexReg, llvm::MachineFunction::insert(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), PHI, llvm::X86AddressMode::Reg, llvm::X86AddressMode::RegBase, llvm::X86AddressMode::Scale, and llvm::MachineBasicBlock::transferSuccessors().

const char * X86TargetLowering::getTargetNodeName

(

unsigned

Opcode

)

const [virtual]

getTargetNodeName - This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 6658 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADD, llvm::X86ISD::ATOMADD64_DAG, llvm::X86ISD::ATOMAND64_DAG, llvm::X86ISD::ATOMNAND64_DAG, llvm::X86ISD::ATOMOR64_DAG, llvm::X86ISD::ATOMSUB64_DAG, llvm::X86ISD::ATOMXOR64_DAG, llvm::X86ISD::BRCOND, llvm::X86ISD::BSF, llvm::X86ISD::BSR, llvm::X86ISD::BT, llvm::X86ISD::CALL, llvm::X86ISD::CMOV, llvm::X86ISD::CMP, llvm::X86ISD::CMPPD, llvm::X86ISD::CMPPS, llvm::X86ISD::COMI, llvm::X86ISD::EH_RETURN, llvm::X86ISD::FAND, llvm::X86ISD::FILD_FLAG, llvm::X86ISD::FLD, llvm::X86ISD::FMAX, llvm::X86ISD::FMIN, llvm::X86ISD::FNSTCW16m, llvm::X86ISD::FOR, llvm::X86ISD::FP_TO_INT16_IN_MEM, llvm::X86ISD::FP_TO_INT32_IN_MEM, llvm::X86ISD::FP_TO_INT64_IN_MEM, llvm::X86ISD::FRCP, llvm::X86ISD::FRSQRT, llvm::X86ISD::FSRL, llvm::X86ISD::FST, llvm::X86ISD::FXOR, llvm::X86ISD::GlobalBaseReg, llvm::X86ISD::INSERTPS, llvm::X86ISD::LCMPXCHG8_DAG, llvm::X86ISD::LCMPXCHG_DAG, llvm::X86ISD::PCMPEQB, llvm::X86ISD::PCMPEQD, llvm::X86ISD::PCMPEQQ, llvm::X86ISD::PCMPEQW, llvm::X86ISD::PCMPGTB, llvm::X86ISD::PCMPGTD, llvm::X86ISD::PCMPGTQ, llvm::X86ISD::PCMPGTW, llvm::X86ISD::PEXTRB, llvm::X86ISD::PEXTRW, llvm::X86ISD::PINSRB, llvm::X86ISD::PINSRW, llvm::X86ISD::RDTSC_DAG, llvm::X86ISD::REP_MOVS, llvm::X86ISD::REP_STOS, llvm::X86ISD::RET_FLAG, llvm::X86ISD::SETCC, llvm::X86ISD::SHLD, llvm::X86ISD::SHRD, llvm::X86ISD::SMUL, llvm::X86ISD::SUB, llvm::X86ISD::TAILCALL, llvm::X86ISD::TC_RETURN, llvm::X86ISD::THREAD_POINTER, llvm::X86ISD::TLSADDR, llvm::X86ISD::UCOMI, llvm::X86ISD::UMUL, llvm::X86ISD::VSHL, llvm::X86ISD::VSRL, llvm::X86ISD::VZEXT_LOAD, llvm::X86ISD::VZEXT_MOVL, and llvm::X86ISD::Wrapper.

MVT X86TargetLowering::getSetCCResultType

(

MVT

VT

)

const [virtual]

getSetCCResultType - Return the ISD::SETCC ValueType

Reimplemented from llvm::TargetLowering.

Definition at line 826 of file X86ISelLowering.cpp.

References llvm::MVT::i8.

void X86TargetLowering::computeMaskedBitsForTargetNode	(	const SDValue	Op,
		const APInt &	Mask,
		APInt &	KnownZero,
		APInt &	KnownOne,
		const SelectionDAG &	DAG,
		unsigned	Depth = 0
	)			const [virtual]

computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Reimplemented from llvm::TargetLowering.

Definition at line 7501 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADD, llvm::ISD::BUILTIN_OP_END, llvm::APInt::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getResNo(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::X86ISD::SETCC, llvm::X86ISD::SMUL, llvm::X86ISD::SUB, and llvm::X86ISD::UMUL.

bool X86TargetLowering::isGAPlusOffset	(	SDNode *	N,
		GlobalValue *&	GA,
		int64_t &	Offset
	)			const [virtual]

isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Reimplemented from llvm::TargetLowering.

Definition at line 7535 of file X86ISelLowering.cpp.

References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLowering::isGAPlusOffset(), and llvm::X86ISD::Wrapper.

SDValue X86TargetLowering::getReturnAddressFrameIndex

(

SelectionDAG &

DAG

)

Definition at line 1970 of file X86ISelLowering.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetData::getPointerSize(), llvm::TargetLowering::getPointerTy(), llvm::X86MachineFunctionInfo::getRAIndex(), and llvm::X86MachineFunctionInfo::setRAIndex().

X86TargetLowering::ConstraintType X86TargetLowering::getConstraintType

(

const std::string &

Constraint

)

const [virtual]

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

Reimplemented from llvm::TargetLowering.

Definition at line 8000 of file X86ISelLowering.cpp.

References llvm::TargetLowering::C_Register, llvm::TargetLowering::C_RegisterClass, and llvm::TargetLowering::getConstraintType().

std::vector< unsigned > X86TargetLowering::getRegClassForInlineAsmConstraint	(	const std::string &	Constraint,
		MVT	VT
	)			const [virtual]

getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), return a list of registers that can be used to satisfy the constraint. This should only be used for C_RegisterClass constraints.

Reimplemented from llvm::TargetLowering.

Definition at line 8128 of file X86ISelLowering.cpp.

References llvm::ARMCC::AL, llvm::XCoreISD::BL, llvm::N86::EAX, llvm::N86::EBX, llvm::N86::EDX, llvm::MVT::i16, llvm::MVT::i32, and llvm::MVT::i8.

const char * X86TargetLowering::LowerXConstraint

(

MVT

ConstraintVT

)

const [virtual]

LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

Reimplemented from llvm::TargetLowering.

Definition at line 8026 of file X86ISelLowering.cpp.

References llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::isFloatingPoint(), and llvm::TargetLowering::LowerXConstraint().

void X86TargetLowering::LowerAsmOperandForConstraint	(	SDValue	Op,
		char	Constraint,
		bool	hasMemory,
		std::vector< SDValue > &	Ops,
		SelectionDAG &	DAG
	)			const [virtual]

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.

Reimplemented from llvm::TargetLowering.

Definition at line 8041 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::dyn_cast(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SDValue::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), and llvm::TargetLowering::LowerAsmOperandForConstraint().

std::pair< unsigned, const TargetRegisterClass * > X86TargetLowering::getRegForInlineAsmConstraint	(	const std::string &	Constraint,
		MVT	VT
	)			const [virtual]

getRegForInlineAsmConstraint - Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register. This should only be used for C_Register constraints. On error, this returns a register number of 0.

Reimplemented from llvm::TargetLowering.

Definition at line 8152 of file X86ISelLowering.cpp.

References llvm::ARMCC::AL, llvm::XCoreISD::BL, llvm::N86::EAX, llvm::N86::EBP, llvm::N86::EBX, llvm::N86::EDI, llvm::N86::EDX, llvm::N86::ESI, llvm::N86::ESP, llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MVT::getSimpleVT(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), isScalarFPTypeInSSEReg(), llvm::StringsEqualNoCase(), llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::MVT::v8i16.

bool X86TargetLowering::isLegalAddressingMode	(	const AddrMode &	AM,
		const Type *	Ty
	)			const [virtual]

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLowering.

Definition at line 6736 of file X86ISelLowering.cpp.

References llvm::TargetLowering::AddrMode::BaseGV, llvm::TargetLowering::AddrMode::BaseOffs, llvm::TargetMachine::getCodeModel(), llvm::TargetLowering::getTargetMachine(), llvm::X86Subtarget::GVRequiresExtraLoad(), llvm::X86Subtarget::GVRequiresRegister(), llvm::TargetLowering::AddrMode::HasBaseReg, llvm::X86Subtarget::is64Bit(), llvm::TargetLowering::AddrMode::Scale, and llvm::CodeModel::Small.

bool X86TargetLowering::isTruncateFree	(	const Type *	Ty1,
		const Type *	Ty2
	)			const [virtual]

isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.

Reimplemented from llvm::TargetLowering.

Definition at line 6787 of file X86ISelLowering.cpp.

References llvm::Type::getPrimitiveSizeInBits(), llvm::X86Subtarget::is64Bit(), and llvm::Type::isInteger().

bool X86TargetLowering::isTruncateFree	(	MVT	VT1,
		MVT	VT2
	)			const [virtual]

Reimplemented from llvm::TargetLowering.

Definition at line 6797 of file X86ISelLowering.cpp.

References llvm::MVT::getSizeInBits(), llvm::X86Subtarget::is64Bit(), and llvm::MVT::isInteger().

bool X86TargetLowering::isShuffleMaskLegal	(	SDValue	Mask,
		MVT	VT
	)			const [virtual]

isShuffleMaskLegal - Targets can use this to indicate that they only support *some* VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

isShuffleMaskLegal - Targets can use this to indicate that they only support *some* VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented from llvm::TargetLowering.

Definition at line 6812 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::MVT::getSizeInBits(), isIdentityMask(), isPSHUFHW_PSHUFLWMask(), isSplatMask(), llvm::X86::isUNPCKH_v_undef_Mask(), llvm::X86::isUNPCKHMask(), llvm::X86::isUNPCKL_v_undef_Mask(), and llvm::X86::isUNPCKLMask().

bool X86TargetLowering::isVectorClearMaskLegal	(	const std::vector< SDValue > &	BVOps,
		MVT	EVT,
		SelectionDAG &	DAG
	)			const [virtual]

isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Reimplemented from llvm::TargetLowering.

Definition at line 6827 of file X86ISelLowering.cpp.

References llvm::MVT::getSizeInBits(), isCommutedMOVL(), isCommutedSHUFP(), isMOVLMask(), and isSHUFPMask().

virtual bool llvm::X86TargetLowering::ShouldShrinkFPConstant

(

MVT

VT

)

const [inline, virtual]

ShouldShrinkFPConstant - If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Reimplemented from llvm::TargetLowering.

Definition at line 472 of file X86ISelLowering.h.

References llvm::MVT::f80.

bool X86TargetLowering::IsEligibleForTailCallOptimization	(	CallSDNode *	TheCall,
		SDValue	Ret,
		SelectionDAG &	DAG
	)			const [virtual]

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization. Target which want to do tail call optimization should implement this function.

IsEligibleForTailCallElimination - Check to see whether the next instruction following the call is a return. A function is eligible if caller/callee calling conventions match, currently only fastcc supports tail calls, and the function CALL is immediatly followed by a RET.

Reimplemented from llvm::TargetLowering.

Definition at line 1917 of file X86ISelLowering.cpp.

References llvm::TargetLowering::CheckTailCallReturnConstraints(), llvm::CallingConv::Fast, llvm::CallSDNode::getCallee(), llvm::CallSDNode::getCallingConv(), llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLowering::getTargetMachine(), llvm::GlobalValue::hasHiddenVisibility(), llvm::GlobalValue::hasProtectedVisibility(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isPICStyleGOT(), and llvm::Reloc::PIC_.

virtual const X86Subtarget* llvm::X86TargetLowering::getSubtarget

(

)

[inline, virtual]

Reimplemented from llvm::TargetLowering.

Definition at line 486 of file X86ISelLowering.h.

bool llvm::X86TargetLowering::isScalarFPTypeInSSEReg

(

MVT

VT

)

const [inline]

isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating point stack.

Definition at line 492 of file X86ISelLowering.h.

References llvm::MVT::f32, and llvm::MVT::f64.

Referenced by getRegForInlineAsmConstraint().

MVT X86TargetLowering::getWidenVectorType

(

MVT

VT

)

const [virtual]

getWidenVectorType: given a vector type, returns the type to widen to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. If there is no vector type that we want to widen to, returns MVT::Other When and were to widen is target dependent based on the cost of scalarizing vs using the wider vector type.

getWidenVectorType: given a vector type, returns the type to widen to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. If there is no vector type that we want to widen to, returns MVT::Other When and where to widen is target dependent based on the cost of scalarizing vs using the wider vector type.

Reimplemented from llvm::TargetLowering.

Definition at line 8316 of file X86ISelLowering.cpp.

References llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::TargetLowering::isTypeLegal(), llvm::MVT::isVector(), llvm::MVT::LAST_VECTOR_VALUETYPE, and llvm::MVT::Other.

FastISel * X86TargetLowering::createFastISel	(	MachineFunction &	mf,
		MachineModuleInfo *	mmi,
		DwarfWriter *	dw,
		DenseMap< const Value *, unsigned > &	vm,
		DenseMap< const BasicBlock *, MachineBasicBlock * > &	bm,
		DenseMap< const AllocaInst *, int > &	am,
		SmallSet< Instruction *, 8 > &	cil
	)			[virtual]

createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented from llvm::TargetLowering.

Definition at line 1946 of file X86ISelLowering.cpp.

References llvm::X86::createFastISel().

---

The documentation for this class was generated from the following files:

• X86ISelLowering.h
• X86ISelLowering.cpp