1.5.6Copyright © 2003-2007 University of Illinois at Urbana-Champaign. All Rights Reserved.
LLVM API Documentation
#include <XCoreInstrInfo.h>
Definition at line 22 of file XCoreInstrInfo.h.
| XCoreInstrInfo::XCoreInstrInfo | ( | void | ) |
Definition at line 39 of file XCoreInstrInfo.cpp.
| virtual const TargetRegisterInfo& llvm::XCoreInstrInfo::getRegisterInfo | ( | ) | const [inline, virtual] |
getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 31 of file XCoreInstrInfo.h.
Referenced by llvm::XCoreTargetMachine::getRegisterInfo().
| bool XCoreInstrInfo::isMoveInstr | ( | const MachineInstr & | MI, | |
| unsigned & | SrcReg, | |||
| unsigned & | DstReg, | |||
| unsigned & | SrcSR, | |||
| unsigned & | DstSR | |||
| ) | const [virtual] |
Return true if the instruction is a register to register move and return the source and dest operands and their sub-register indices by reference.
Return true if the instruction is a register to register move and leave the source and dest operands in the passed parameters.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 51 of file XCoreInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and isZeroImm().
| unsigned XCoreInstrInfo::isLoadFromStackSlot | ( | const MachineInstr * | MI, | |
| int & | FrameIndex | |||
| ) | const [virtual] |
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 81 of file XCoreInstrInfo.cpp.
References llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and isZeroImm().
Referenced by isInvariantLoad().
| unsigned XCoreInstrInfo::isStoreToStackSlot | ( | const MachineInstr * | MI, | |
| int & | FrameIndex | |||
| ) | const [virtual] |
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 102 of file XCoreInstrInfo.cpp.
References llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and isZeroImm().
| bool XCoreInstrInfo::isInvariantLoad | ( | const MachineInstr * | MI | ) | const [virtual] |
isInvariantLoad - Return true if the specified instruction (which is marked mayLoad) is loading from a location whose value is invariant across the function. For example, loading a value from the constant pool or from from the argument area of a function if it does not change. This should only return true of *all* loads the instruction does are invariant (if it does multiple loads).
Reimplemented from llvm::TargetInstrInfo.
Definition at line 125 of file XCoreInstrInfo.cpp.
References FrameIndex, llvm::MachineFunction::getFrameInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::isCPI(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::MachineFrameInfo::isImmutableObjectIndex(), isLoadFromStackSlot(), and MFI.
| bool XCoreInstrInfo::AnalyzeBranch | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock *& | TBB, | |||
| MachineBasicBlock *& | FBB, | |||
| SmallVectorImpl< MachineOperand > & | Cond, | |||
| bool | AllowModify | |||
| ) | const [virtual] |
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null. 2. If this block ends with only an unconditional branch, it sets TBB to be the destination block. 3. If this block ends with an conditional branch and it falls through to an successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. 4. If this block ends with an conditional branch and an unconditional block, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
Note that RemoveBranch and InsertBranch must be implemented to support cases where this method returns success.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 230 of file XCoreInstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::XCore::COND_INVALID, llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), GetCondFromBranchOpc(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), IsBRU(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), and llvm::SmallVectorImpl< T >::push_back().
| unsigned XCoreInstrInfo::InsertBranch | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock * | TBB, | |||
| MachineBasicBlock * | FBB, | |||
| const SmallVectorImpl< MachineOperand > & | Cond | |||
| ) | const [virtual] |
InsertBranch - Insert a branch into the end of the specified MachineBasicBlock. This operands to this method are the same as those returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch returns success and when an unconditional branch (TBB is non-null, FBB is null, Cond is empty) needs to be inserted. It returns the number of instructions inserted.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 302 of file XCoreInstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::SmallVectorImpl< T >::empty(), GetCondBranchFromCond(), and llvm::SmallVectorImpl< T >::size().
| unsigned XCoreInstrInfo::RemoveBranch | ( | MachineBasicBlock & | MBB | ) | const [virtual] |
RemoveBranch - Remove the branching code at the end of the specific MBB. This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions that were removed.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 333 of file XCoreInstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), IsBRU(), and IsCondBranch().
| bool XCoreInstrInfo::copyRegToReg | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | DestReg, | |||
| unsigned | SrcReg, | |||
| const TargetRegisterClass * | DestRC, | |||
| const TargetRegisterClass * | SrcRC | |||
| ) | const [virtual] |
copyRegToReg - Emit instructions to copy between a pair of registers. It returns false if the target does not how to copy between the specified registers.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 355 of file XCoreInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), and llvm::BuildMI().
| void XCoreInstrInfo::storeRegToStackSlot | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | SrcReg, | |||
| bool | isKill, | |||
| int | FrameIndex, | |||
| const TargetRegisterClass * | RC | |||
| ) | const [virtual] |
storeRegToStackSlot - Store the specified register of the given register class to the specified stack frame index. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 382 of file XCoreInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), and llvm::BuildMI().
Referenced by spillCalleeSavedRegisters().
| void XCoreInstrInfo::storeRegToAddr | ( | MachineFunction & | MF, | |
| unsigned | SrcReg, | |||
| bool | isKill, | |||
| SmallVectorImpl< MachineOperand > & | Addr, | |||
| const TargetRegisterClass * | RC, | |||
| SmallVectorImpl< MachineInstr * > & | NewMIs | |||
| ) | const [virtual] |
storeRegToAddr - Store the specified register of the given register class to the specified address. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 391 of file XCoreInstrInfo.cpp.
| void XCoreInstrInfo::loadRegFromStackSlot | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | DestReg, | |||
| int | FrameIndex, | |||
| const TargetRegisterClass * | RC | |||
| ) | const [virtual] |
loadRegFromStackSlot - Load the specified register of the given register class from the specified stack frame index. The load instruction is to be added to the given machine basic block before the specified machine instruction.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 399 of file XCoreInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), and llvm::BuildMI().
Referenced by restoreCalleeSavedRegisters().
| void XCoreInstrInfo::loadRegFromAddr | ( | MachineFunction & | MF, | |
| unsigned | DestReg, | |||
| SmallVectorImpl< MachineOperand > & | Addr, | |||
| const TargetRegisterClass * | RC, | |||
| SmallVectorImpl< MachineInstr * > & | NewMIs | |||
| ) | const [virtual] |
loadRegFromAddr - Load the specified register of the given register class class from the specified address. The load instruction is to be added to the given machine basic block before the specified machine instruction.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 408 of file XCoreInstrInfo.cpp.
| bool XCoreInstrInfo::spillCalleeSavedRegisters | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| const std::vector< CalleeSavedInfo > & | CSI | |||
| ) | const [virtual] |
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns true if it isn't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot(). Returns false otherwise.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 416 of file XCoreInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::BuildMI(), llvm::ISD::DBG_LABEL, llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::getMachineModuleInfo(), llvm::MachineBasicBlock::getParent(), llvm::XCoreFunctionInfo::getSpillLabels(), MF, MFI, MMI, llvm::XCoreRegisterInfo::needsFrameMoves(), llvm::MachineModuleInfo::NextLabelID(), and storeRegToStackSlot().
| bool XCoreInstrInfo::restoreCalleeSavedRegisters | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| const std::vector< CalleeSavedInfo > & | CSI | |||
| ) | const [virtual] |
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns true if it isn't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot(). Returns false otherwise.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 447 of file XCoreInstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), and loadRegFromStackSlot().
| bool XCoreInstrInfo::BlockHasNoFallThrough | ( | const MachineBasicBlock & | MBB | ) | const [virtual] |
BlockHasNoFallThrough - Analyse if MachineBasicBlock does not fall-through into its successor block.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 478 of file XCoreInstrInfo.cpp.
References llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::empty(), and llvm::MachineInstr::getOpcode().
| bool XCoreInstrInfo::ReverseBranchCondition | ( | SmallVectorImpl< MachineOperand > & | Cond | ) | const [virtual] |
ReverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 498 of file XCoreInstrInfo.cpp.
References GetOppositeBranchCondition(), and llvm::SmallVectorImpl< T >::size().
Generated on Thu Nov 5 23:53:46 2009 for LLVM by
1.5.6
Copyright © 2003-2007 University of Illinois at Urbana-Champaign.
All Rights Reserved.