llvm::X86 Namespace Reference

Define some predicates that are used for node matching. More...

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

enum llvm::X86::CondCode

Enumerator:

COND_A
COND_AE
COND_B
COND_BE
COND_E
COND_G
COND_GE
COND_L
COND_LE
COND_NE
COND_NO
COND_NP
COND_NS
COND_O
COND_P
COND_S
COND_NE_OR_P
COND_NP_OR_E
COND_INVALID

Definition at line 30 of file X86InstrInfo.h.

enum llvm::X86::RelocationType

RelocationType - An enum for the x86 relocation codes. Note that the terminology here doesn't follow x86 convention - word means 32-bit and dword means 64-bit.

Enumerator:

reloc_pcrel_word
reloc_picrel_word
reloc_absolute_word
reloc_absolute_dword

Definition at line 24 of file X86Relocations.h.

enum llvm::X86::SubregIndex

SubregIndex - The index of various sized subregister classes. Note that these indices must be kept in sync with the class indices in the X86RegisterInfo.td file.

Enumerator:

SUBREG_8BIT
SUBREG_16BIT
SUBREG_32BIT

Definition at line 37 of file X86RegisterInfo.h.

Function Documentation

llvm::FastISel * llvm::X86::createFastISel	(	MachineFunction &	mf,
		MachineModuleInfo *	mmi,
		DwarfWriter *	dw,
		DenseMap< const Value *, unsigned > &	vm,
		DenseMap< const BasicBlock , MachineBasicBlock > &	bm,
		DenseMap< const AllocaInst *, int > &	am,
		SmallSet< Instruction *, 8 > &	cil
	)

Definition at line 1515 of file X86FastISel.cpp.

Referenced by llvm::X86TargetLowering::createFastISel().

unsigned llvm::X86::GetCondBranchFromCond ( X86::CondCode CC )

Definition at line 1422 of file X86InstrInfo.cpp.

References COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_G, COND_GE, COND_L, COND_LE, COND_NE, COND_NO, COND_NP, COND_NS, COND_O, COND_P, and COND_S.

bool llvm::X86::GetCpuIDAndInfo	(	unsigned	value,
		unsigned *	rEAX,
		unsigned *	rEBX,
		unsigned *	rECX,
		unsigned *	rEDX
	)

GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the specified arguments. If we can't run cpuid on the host, return true.

Definition at line 111 of file X86Subtarget.cpp.

Referenced by llvm::X86Subtarget::AutoDetectSubtargetFeatures(), GetCurrentX86CPU(), and llvm::X86JITInfo::getLazyResolverFunction().

X86::CondCode llvm::X86::GetOppositeBranchCondition ( X86::CondCode CC )

GetOppositeBranchCondition - Return the inverse of the specified cond, e.g. turning COND_E to COND_NE.

GetOppositeBranchCondition - Return the inverse of the specified condition, e.g. turning COND_E to COND_NE.

Definition at line 1446 of file X86InstrInfo.cpp.

References COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_G, COND_GE, COND_L, COND_LE, COND_NE, COND_NO, COND_NP, COND_NS, COND_O, COND_P, and COND_S.

unsigned llvm::X86::getShufflePSHUFHWImmediate ( SDNode * N )

getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW instructions.

Definition at line 2640 of file X86ISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.

unsigned llvm::X86::getShufflePSHUFLWImmediate ( SDNode * N )

getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW instructions.

getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW instructions.

Definition at line 2659 of file X86ISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.

unsigned llvm::X86::getShuffleSHUFImmediate ( SDNode * N )

getShuffleSHUFImmediate - Return the appropriate immediate to shuffle the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.

Definition at line 2619 of file X86ISelLowering.cpp.

References llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.

bool llvm::X86::isMOVDDUPMask ( SDNode * N )

isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVDDUP.

Definition at line 2603 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isUndefOrEqual().

bool llvm::X86::isMOVHLPS_v_undef_Mask ( SDNode * N )

isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, <2, 3, 2, 3>

Definition at line 2241 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isUndefOrEqual().

bool llvm::X86::isMOVHLPSMask ( SDNode * N )

isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVHLPS.

Definition at line 2225 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isUndefOrEqual().

bool llvm::X86::isMOVHPMask ( SDNode * N )

isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVHP{S|D} as well as MOVLHPS.

isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVHP{S|D} and MOVLHPS.

Definition at line 2277 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isUndefOrEqual().

bool llvm::X86::isMOVLMask ( SDNode * N )

isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSS, MOVSD, and MOVD, i.e. setting the lowest element.

Definition at line 2422 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), isMOVLMask(), and llvm::SDNode::op_begin().

bool llvm::X86::isMOVLPMask ( SDNode * N )

isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.

Definition at line 2256 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isUndefOrEqual().

bool llvm::X86::isMOVSHDUPMask ( SDNode * N )

isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSHDUP.

Definition at line 2460 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.

bool llvm::X86::isMOVSLDUPMask ( SDNode * N )

isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSLDUP.

Definition at line 2491 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.

bool llvm::X86::isPSHUFDMask ( SDNode * N )

isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to PSHUFD.

Definition at line 2109 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.

bool llvm::X86::isPSHUFHWMask ( SDNode * N )

isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to PSHUFD.

isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to PSHUFHW.

Definition at line 2129 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.

bool llvm::X86::isPSHUFLWMask ( SDNode * N )

isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to PSHUFD.

isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to PSHUFLW.

Definition at line 2159 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), isUndefOrEqual(), and isUndefOrInRange().

bool llvm::X86::isSHUFPMask ( SDNode * N )

isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to SHUFP*.

Definition at line 2195 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), isSHUFPMask(), and llvm::SDNode::op_begin().

bool llvm::X86::isSplatLoMask ( SDNode * N )

isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of zero element.

Definition at line 2592 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isUndefOrEqual().

bool llvm::X86::isSplatMask ( SDNode * N )

isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element.

isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element and it's a 2 or 4 element mask.

Definition at line 2581 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), and isSplatMask().

Referenced by getSplatMaskEltNo().

bool llvm::X86::isUNPCKH_v_undef_Mask ( SDNode * N )

isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, <2, 2, 3, 3>

Definition at line 2383 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isUndefOrEqual().

Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().

bool llvm::X86::isUNPCKHMask	(	SDNode *	N,
		bool	V2IsSplat = `false`
	)

isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKH.

Definition at line 2352 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), isUNPCKHMask(), and llvm::SDNode::op_begin().

Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().

bool llvm::X86::isUNPCKL_v_undef_Mask ( SDNode * N )

isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, <0, 0, 1, 1>

Definition at line 2360 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isUndefOrEqual().

Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().

bool llvm::X86::isUNPCKLMask	(	SDNode *	N,
		bool	V2IsSplat = `false`
	)

isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKL.

Definition at line 2322 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), isUNPCKLMask(), and llvm::SDNode::op_begin().

Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().


Enumerations
enum	CondCode { COND_A = 0, COND_AE = 1, COND_B = 2, COND_BE = 3, COND_E = 4, COND_G = 5, COND_GE = 6, COND_L = 7, COND_LE = 8, COND_NE = 9, COND_NO = 10, COND_NP = 11, COND_NS = 12, COND_O = 13, COND_P = 14, COND_S = 15, COND_NE_OR_P, COND_NP_OR_E, COND_INVALID }
enum	SubregIndex { SUBREG_8BIT = 1, SUBREG_16BIT = 2, SUBREG_32BIT = 3 }
enum	RelocationType { reloc_pcrel_word = 0, reloc_picrel_word = 1, reloc_absolute_word = 2, reloc_absolute_dword = 3 }
Functions
unsigned	GetCondBranchFromCond (CondCode CC)
CondCode	GetOppositeBranchCondition (X86::CondCode CC)
bool	isPSHUFDMask (SDNode *N)
bool	isPSHUFHWMask (SDNode *N)
bool	isPSHUFLWMask (SDNode *N)
bool	isSHUFPMask (SDNode *N)
bool	isMOVHLPSMask (SDNode *N)
bool	isMOVHLPS_v_undef_Mask (SDNode *N)
bool	isMOVLPMask (SDNode *N)
bool	isMOVHPMask (SDNode *N)
bool	isUNPCKLMask (SDNode *N, bool V2IsSplat=false)
bool	isUNPCKHMask (SDNode *N, bool V2IsSplat=false)
bool	isUNPCKL_v_undef_Mask (SDNode *N)
bool	isUNPCKH_v_undef_Mask (SDNode *N)
bool	isMOVLMask (SDNode *N)
bool	isMOVSHDUPMask (SDNode *N)
bool	isMOVSLDUPMask (SDNode *N)
bool	isSplatMask (SDNode *N)
bool	isSplatLoMask (SDNode *N)
bool	isMOVDDUPMask (SDNode *N)
unsigned	getShuffleSHUFImmediate (SDNode *N)
unsigned	getShufflePSHUFHWImmediate (SDNode *N)
unsigned	getShufflePSHUFLWImmediate (SDNode *N)
FastISel *	createFastISel (MachineFunction &mf, MachineModuleInfo mmi, DwarfWriter dw, DenseMap< const Value , unsigned > &, DenseMap< const BasicBlock , MachineBasicBlock * > &, DenseMap< const AllocaInst , int > &, SmallSet< Instruction , 8 > &)
bool	GetCpuIDAndInfo (unsigned value, unsigned rEAX, unsigned rEBX, unsigned rECX, unsigned rEDX)

llvm::X86 Namespace Reference

Enumerations

Functions

Detailed Description

Enumeration Type Documentation

Function Documentation